HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet
HD64F7047F50
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HD64F7047F50 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH-2 SH7047 Group 32 Hardware Manual Renesas ...
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Rev. 2.00, 09/04, page ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The SH7047 group single-chip RISC (Reduced Instruction Set Computer) microprocessor includes a Renesas -original RISC CPU as its core, and the peripheral functions required to configure a system. Target users: This manual was written for users who will be using ...
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The typical product The HD64F7047 is taken as the typical product for the descriptions in this manual. Accordingly, when using an HD6437049, simply replace the HD64F7047 in those references where no differences between products are pointed out with HD6437049. ...
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Users manuals for development tools: Document Title SuperH RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual SuperH RISC engine Simulator/Debugger User's Manual High-performance Embedded Workshop User's Manual Rev. 2.00, 09/04, page viii of xl Document No. ADE-702-372 ADE-702-186 ...
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Section 1 Overview............................................................................................1 1.1 Features............................................................................................................................. 2 1.2 Internal Block Diagram..................................................................................................... 4 1.3 Pin Arrangement ............................................................................................................... 5 1.4 Pin Functions .................................................................................................................... 6 Section 2 CPU....................................................................................................13 2.1 Features............................................................................................................................. 13 2.2 Register Configuration...................................................................................................... 14 2.2.1 General Registers (Rn)......................................................................................... 14 2.2.2 Control Registers ................................................................................................. ...
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Section 4 Clock Pulse Generator....................................................................... 51 4.1 Oscillator........................................................................................................................... 52 4.1.1 Connecting a Crystal Resonator........................................................................... 52 4.1.2 External Clock Input Method .............................................................................. 53 4.2 Function for Detecting the Oscillator Halt........................................................................ 54 4.3 Usage Notes ...................................................................................................................... 55 4.3.1 Note on Crystal Resonator................................................................................... ...
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Interrupt Control Register 1 (ICR1)..................................................................... 76 6.3.2 Interrupt Control Register 2 (ICR2)..................................................................... 77 6.3.3 IRQ Status Register (ISR).................................................................................... 79 6.3.4 Interrupt Priority Registers (IPRA, IPRD to IPRI, IPRK) ............... 80 6.4 Interrupt Sources............................................................................................................... 82 ...
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Section 8 Data Transfer Controller (DTC)........................................................ 109 8.1 Features............................................................................................................................. 109 8.2 Register Descriptions........................................................................................................ 111 8.2.1 DTC Mode Register (DTMR).............................................................................. 112 8.2.2 DTC Source Address Register (DTSAR) ............................................................ 114 8.2.3 DTC Destination Address Register (DTDAR) .................................................... 114 8.2.4 DTC Initial Address ...
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Prevention of Data Bus Conflicts......................................................................... 145 9.7.2 Simplification of Bus Cycle Start Detection........................................................ 145 9.8 Bus Arbitration.................................................................................................................. 146 9.9 Memory Connection Example .......................................................................................... 147 9.10 On-chip Peripheral I/O Register Access ........................................................................... 148 9.11 Cycles in which Bus is not ...
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Input/Output Timing............................................................................................ 250 10.6.2 Interrupt Signal Timing ....................................................................................... 255 10.7 Usage Notes ...................................................................................................................... 258 10.7.1 Module Standby Mode Setting ............................................................................ 258 10.7.2 Input Clock Restrictions ...................................................................................... 258 10.7.3 Caution on Period Setting .................................................................................... 259 10.7.4 Contention between TCNT Write ...
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Timer Counter (TCNT)........................................................................................ 319 11.3.2 Timer Control/Status Register (TCSR)................................................................ 319 11.3.3 Reset Control/Status Register (RSTCSR)............................................................ 321 11.4 Operation .......................................................................................................................... 322 11.4.1 Watchdog Timer Mode ........................................................................................ 322 11.4.2 Interval Timer Mode............................................................................................ 323 11.4.3 Clearing Software Standby Mode ........................................................................ 324 11.4.4 ...
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Multiprocessor Serial Data Reception ................................................................. 365 12.6 Operation in Clocked Synchronous Mode ........................................................................ 368 12.6.1 Clock.................................................................................................................... 368 12.6.2 SCI initialization (Clocked Synchronous mode) ................................................. 368 12.6.3 Serial data transmission (Clocked Synchronous mode)....................................... 369 12.6.4 Serial data reception (Clocked Synchronous ...
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Notes on Board Design ........................................................................................ 395 13.7.6 Notes on Noise Countermeasures ........................................................................ 395 Section 14 Compare Match Timer (CMT) ........................................................397 14.1 Features............................................................................................................................. 397 14.2 Register Descriptions ........................................................................................................ 398 14.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 398 14.2.2 Compare ...
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Timer Counter Register (TCNTR)....................................................................... 454 15.3.18 Timer Control Register (TCR)............................................................................. 455 15.3.19 Timer Status Register (TSR)................................................................................ 457 15.3.20 Local Offset Register (LOSR) ............................................................................. 458 15.3.21 Input Capture Registers 0 and 1 (ICR0, ICR1).................................................... 459 15.3.22 Timer Compare Match Registers ...
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Timer Counter (MMT_TCNT) ............................................................................ 490 16.3.5 Timer Buffer Registers (TBR) ............................................................................. 490 16.3.6 Timer General Registers (TGR)........................................................................... 490 16.3.7 Timer Dead Time Counters (TDCNT)................................................................. 490 16.3.8 Timer Dead Time Data Register (MMT_TDDR) ................................................ 490 16.3.9 Timer Period Buffer Register ...
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Port D................................................................................................................................ 541 18.3.1 Register Descriptions........................................................................................... 541 18.3.2 Port D Data Register L (PDDRL)........................................................................ 541 18.4 Port E ................................................................................................................................ 543 18.4.1 Register Descriptions........................................................................................... 544 18.4.2 Port E Data Registers H and L (PEDRH and PEDRL) ........................................ 544 18.5 Port ...
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Section 22 High-Performance User Debugging Interface (H-UDI) .................581 22.1 Overview........................................................................................................................... 581 22.1.1 Features................................................................................................................ 581 22.1.2 Block Diagram..................................................................................................... 582 22.2 Input/Output Pins .............................................................................................................. 583 22.3 Register Description.......................................................................................................... 583 22.3.1 Instruction Register (SDIR) ................................................................................. 584 22.3.2 Status Register (SDSR)........................................................................................ 585 22.3.3 Data ...
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Sleep Mode .......................................................................................................... 611 24.3.2 Software Standby Mode....................................................................................... 611 24.3.3 Hardware Standby Mode ..................................................................................... 614 24.3.4 Module Standby Mode......................................................................................... 615 24.4 Usage Notes ...................................................................................................................... 615 24.4.1 I/O Port Status...................................................................................................... 615 24.4.2 Current Consumption during Oscillation Stabilization Wait Period.................... 616 ...
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Appendix D Package Dimensions .....................................................................703 Main Revisions and Additions in this Edition .....................................................705 Index ...................................................................................................................717 Rev. 2.00, 09/04, page xxiii of xl ...
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Rev. 2.00, 09/04, page xxiv of xl ...
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Section 1 Overview Figure 1.1 Block Diagram of SH7047 ............................................................................................ 4 Figure 1.2 SH7047 Pin Arrangement.............................................................................................. 5 Section 2 CPU Figure 2.1 CPU Internal Registers ................................................................................................ 15 Figure 2.2 Data Format in Registers ............................................................................................. 18 Figure 2.3 Data Formats in ...
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Figure 8.9 Chain Transfer........................................................................................................... 126 Figure 8.10 DTC Operation Timing Example (Normal Mode) .................................................. 127 Section 9 Bus State Controller (BSC) Figure 9.1 BSC Block Diagram.................................................................................................. 134 Figure 9.2 Address Format ......................................................................................................... 136 Figure 9.3 Basic Timing of External Space ...
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Figure 10.28 Example of Phase Counting Mode 4 Operation .................................................... 216 Figure 10.29 Phase Counting Mode Application Example......................................................... 217 Figure 10.30 Procedure for Selecting the Reset-Synchronized PWM Mode.............................. 220 Figure 10.31 Reset-Synchronized PWM Mode Operation Example (When the TOCR’s OLSN ...
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Figure 10.69 Timing for Status Flag Clearing by DTC Activation ............................................ 257 Figure 10.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 258 Figure 10.71 Contention between TCNT Write and Clear Operations....................................... 259 Figure 10.72 Contention between ...
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Figure 10.106 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 .................................................................................................. 298 Figure 10.107 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode .......................................................... 299 Figure 10.108 Error Occurrence in Complementary PWM Mode, Recovery in ...
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Figure 12.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 358 Figure 12.9 Sample Serial Reception Data Flowchart (1) .......................................................... 360 Figure 12.9 Sample Serial Reception Data Flowchart (2) .......................................................... 361 Figure 12.10 ...
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Figure 15.4 Extended Format ..................................................................................................... 447 Figure 15.5 Hardware Reset Flowchart ...................................................................................... 461 Figure 15.6 Software Reset Flowchart........................................................................................ 462 Figure 15.7 Detailed Description of 1-Bit Time ......................................................................... 463 Figure 15.8 Transmission Flowchart by Event Trigger .............................................................. 466 Figure 15.9 Transmit ...
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Figure 19.2 Flash Memory State Transitions.............................................................................. 551 Figure 19.3 Boot Mode............................................................................................................... 552 Figure 19.4 User Program Mode ................................................................................................ 553 Figure 19.5 Flash Memory Block Configuration........................................................................ 554 Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode ........................ 562 Figure 19.7 Flowchart ...
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Figure 25.7 Interrupt Signal Input Timing.................................................................................. 628 Figure 25.8 Interrupt Signal Output Timing ............................................................................... 628 Figure 25.9 Bus Release Timing................................................................................................. 628 Figure 25.10 Basic Cycle (No Waits) ......................................................................................... 630 Figure 25.11 Basic Cycle (One Software Wait) ......................................................................... 631 Figure 25.12 ...
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Rev. 2.00, 09/04, page xxxiv of xl ...
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Section 2 CPU Table 2.1 Initial Values of Registers....................................................................................... 17 Table 2.2 Sign Extension of Word Data ................................................................................. 20 Table 2.3 Delayed Branch Instructions................................................................................... 20 Table 2.4 T Bit ........................................................................................................................ 21 Table 2.5 Immediate Data Accessing ..................................................................................... 21 Table 2.6 ...
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Table 8.3 Repeat Mode Register Functions .......................................................................... 124 Table 8.4 Block Transfer Mode Register Functions ............................................................. 125 Table 8.5 Execution State of DTC........................................................................................ 128 Table 8.6 State Counts Needed for Execution State ............................................................. 128 Section 9 Bus State Controller (BSC) ...
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Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 2.................................. 214 Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 3.................................. 215 Table 10.36 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 216 Table 10.37 Output Pins for Reset-Synchronized PWM Mode ............................................ 218 ...
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Section 15 Controller Area Network 2 (HCAN2) Table 15.1 HCAN2 Pins ......................................................................................................... 410 Table 15.2 Mailbox Configuration Bit Setting ....................................................................... 453 Table 15.3 Message Data Area Configuration in TCT Bit Setting ......................................... 454 Table 15.4 Limits on BCR Settable Values ...
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Section 24 Power-Down Modes Table 24.1 Internal Operation States in Each Mode ............................................................... 604 Table 24.2 Pin Configuration.................................................................................................. 606 Section 25 Electrical Characteristics Table 25.1 Absolute Maximum Ratings ................................................................................. 619 Table 25.2 DC Characteristics ................................................................................................ 620 Table 25.3 Permitted Output ...
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Rev. 2.00, 09/04, page ...
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The SH7047 group single-chip RISC (Reduced Instruction Set Computer) microprocessors integrate a Renesas-original RISC CPU core with peripheral functions required for system configuration. The SH7047 group CPU has a RISC-type instruction set. Most instructions can be executed in one state ...
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Features • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Sixteen 32-bit general registers ...
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... On-chip memory ROM Model Flash memory Version HD64F7047 Mask ROM Version HD6437049 • Maximum operating frequency and operating temperature range Model HD64F7047F50/HD6437049F50 HD64F7047FW40/HD6437049FW40 HD64F7047FJ40/HD6437049FJ40 • I/O ports Model HD64F7047/HD6437049 • Supports various power-down states • Compact package Model HD64F7047/HD6437049 ROM ...
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Internal Block Diagram RES WDTOVF HSTBY MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVcL PLL PLLCAP PLLVss VcL VcL FWP Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss AVcc AVcc AVss AVss DBGMD *1 ASEBRKAK *1 Notes: *1 ...
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Pin Arrangement PD8/UBCTRG PD7/D7/AUDSYNC 78 79 PD6/D6/AUDCK 80 PD5/D5/AUDMD 81 PD4/D4/AUDRST FWP HSTBY 85 PD3/D3/AUDATA3 86 RES 87 88 PD2/D2/SCK2/AUDATA2 89 NMI PD1/D1/TXD2/AUDATA1 90 MD3 ...
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Pin Functions Type Symbol Power VCC Supply VSS VCL Clock PLLVCL PLLVSS PLLCAP EXTAL XTAL CK Rev. 2.00, 09/04, page 6 of 720 I/O Name Function Input Power supply Power supply pins. Connect all these pins to the system ...
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Type Symbol Operating MD3 mode control MD2 MD1 MD0 FWP RES System control MRES HSTBY WDTOVF BREQ BACK Interrupts NMI IRQ3 IRQ2 IRQ1 IRQ0 IRQOUT Address bus A17 to A0 Data bus I/O Name Function Input Set ...
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Type Symbol CS0 Bus control RD WRL WAIT Multi function TCLKA timer-pulse TCLKB unit (MTU) TCLKC TCLKD TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Serial com- TxD2 munication TxD3 Interface TxD4 ...
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Type Symbol HCAN2 HTxD1 HRxD1 Motor PUOA management timer PUOB (MMT) PVOA PVOB PWOA PWOB PCIO POE6 to Output POE0 control for MTU and MMT A/D AN15 to AN0 Input converter ADTRG AVCC AVSS I/O Name Function Output Transmitted The ...
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Type Symbol I/O ports PA15 to PA0 Input/ PB5 to PB0 PD8 to PD0 PE21 to PE0 Input/ PF15 to PF0 UBCTRG User break controller (UBC) (flash memory version only) High- TCK performance TMS user debug interface TDI (H-UDI) (flash ...
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Type Symbol ASEBRKAK E10 interface (flash memory version only) DBGMD I/O Name Function Output Break mode Shows that E10A has entered to the break acknowledge mode. Refer to “E10A emulator user’s manual for SH7047” for the detail of the connection ...
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Rev. 2.00, 09/04, page 12 of 720 ...
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Features • General-register architecture Sixteen 32-bit general registers • Sixty-two basic instructions • Eleven addressing modes Register direct [Rn] Register indirect [@Rn] Register indirect with post-increment [@Rn+] Register indirect with pre-decrement [@-Rn] Register ...
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Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. 2.2.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0–R15. General registers are used for data ...
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General registers (Rn) Status register (SR) Global base register (GBR) Vector base register (VBR) Multiply-accumulate register (MAC) Procedure register (PR) Program counter (PC) Notes functions as an index register in the indirect indexed register addressing mode and indirect ...
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Control Registers The control registers consist of three 32-bit registers: status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the ...
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System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). Multiply-and-Accumulate Registers (MAC): Registers to store the results of multiply-and- accumulate ...
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Data Formats 2.3.1 Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits word (16 bits changed into a longword by expanding the ...
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Immediate Data Format Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, ...
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Instruction Features 2.4.1 RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per State: The microprocessor can execute basic instructions ...
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Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations are executed in one to two states. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate operations are executed in two to three states. 32-bit × 32-bit → 64-bit multiply and 32-bit ...
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Absolute Address: When data is accessed by absolute address, the value in the absolute address is placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the ...
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Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Direct register Rn addressing Indirect register @Rn addressing Post-increment @Rn+ indirect register addressing Pre-decrement @-Rn indirect register ...
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Addressing Instruction Mode Format Indirect register @(disp:4, addressing with Rn) displacement Indirect indexed @(R0, Rn) The effective address is the sum of Rn and R0. register addressing Indirect GBR @(disp:8, addressing with GBR) displacement Indirect indexed @(R0, GBR GBR) addressing ...
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Addressing Instruction Mode Format Indirect PC @(disp:8, addressing with PC) displacement PC relative disp:8 addressing disp:12 Effective Address Calculation The effective address is the sum of PC value and an 8-bit displacement (disp). The value of disp is zero-extended, and ...
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Addressing Instruction Mode Format PC relative Rn addressing Immediate #imm:8 addressing #imm:8 #imm:8 2.4.3 Instruction Format The instruction formats and the meaning of source and destination operand are described below. The meaning of the operand depends on the instruction code. ...
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Table 2.9 Instruction Formats Instruction Formats 0 format 15 xxxx xxxx xxxx xxxx n format 15 xxxx nnnn xxxx xxxx m format 15 xxxx mmmm xxxx xxxx nm format 15 xxxx nnnn xxxx mmmm Source Destination Operand Operand ...
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Instruction Formats md format 15 xxxx xxxx dddd mmmm nd4 format 15 xxxx xxxx nnnn dddd nmd format 15 xxxx nnnn dddd mmmm d format 15 xxxx xxxx dddd dddd d12 format 15 xxxx dddd dddd dddd nd8 format 15 ...
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Instruction Set 2.5.1 Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Operation Classification Types Code Data transfer 5 MOV MOVA MOVT SWAP XTRCT Arithmetic 21 ADD operations ADDC ADDV ...
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Operation Classification Types Code Arithmetic SUBC operations SUBV Logic 6 AND operations NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRA BRAF BSR BSRF JMP JSR RTS ...
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Operation Classification Types Code System 11 CLRT control CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 The table below shows the format of instruction codes, operation, and execution states. They are described by using this format ...
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Instruction Code Format: Item Format Instruction Described in mnemonic. OP.Sz SRC,DEST Described in MSB ↔ Instruction code LSB order →, ← Outline of the Operation (xx) M/Q/T & <<n >>n Execution states T bit Notes: ...
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Data Transfer Instructions: Instruction MOV #imm,Rn MOV.W @(disp,PC),Rn 1001nnnndddddddd MOV.L @(disp,PC),Rn 1101nnnndddddddd MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) ...
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Instruction MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp,GBR) 11000000dddddddd MOV.W R0,@(disp,GBR) 11000001dddddddd MOV.L R0,@(disp,GBR) 11000010dddddddd MOV.B @(disp,GBR),R0 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 11000111dddddddd MOVT Rn SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn Rev. 2.00, 09/04, page ...
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Arithmetic Operation Instructions: Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 CMP/PL Rn 0100nnnn00010101 CMP/PZ ...
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Instruction Instruction Code DT Rn 0100nnnn00010000 EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 SUB ...
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Logic Operation Instructions: Instruction AND Rm,Rn AND #imm,R0 AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm → NOT Rm,Rn OR Rm,Rn OR #imm,R0 #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm → OR.B TAS.B @Rn TST Rm,Rn TST #imm,R0 TST.B #imm,@(R0,GBR) ...
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Shift Instructions: Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 SHLR8 Rn ...
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Branch Instructions: Instruction Instruction Code BF label 10001011dddddddd BF/S label 10001111dddddddd BT label 10001001dddddddd BT/S label 10001101dddddddd BRA label 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR label 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 JSR @Rm 0100mmmm00001011 RTS 0000000000001011 Note: * One ...
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System Control Instructions: Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L @Rm+,MACH 0100mmmm00000110 ...
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Instruction Instruction Code STS.L PR,@–Rn 0100nnnn00100010 TRAPA #imm 11000011iiiiiiii Note: * The number of execution states before the chip enters sleep mode: The execution states shown in the table are minimums. The actual number of states may be increased when ...
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Processing States 2.6.1 State Transitions The CPU has five processing states: reset, exception processing, bus release, program execution and power-down. Figure 2.4 shows the transitions between the states. From any state when RES = 0 and HSTBY = 1 ...
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Reset State: The CPU resets in the reset state. When the RES pin level goes low, the power-on reset state is entered. When the RES pin is high and the MRES pin is low, the manual reset state is entered. ...
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Rev. 2.00, 09/04, page 44 of 720 ...
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Section 3 MCU Operating Modes 3.1 Selection of Operating Modes This LSI has four operating modes and four clock modes. The operating mode is determined by the setting of MD3–MD0, and FWP pins. Do not change these pins during LSI ...
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The clock mode is selected by the input of MD2 and MD3 pins. Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode Pin Setting MD3 MD2 Note: The frequencies for the ...
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Explanation of Operating Modes 3.3.1 Mode 0 (MCU extension mode 0) CS0 area becomes an external memory space with 8-bit bus width in this mode. 3.3.2 Mode 1 (MCU extension mode 1) This mode is not supported in this ...
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Address Map The address map for the operating modes are shown in figures 3.1 and 3.2. Mode 0 H'00000000 CS0 area H'0003FFFF H'00040000 Reserved area H'FFFF7FFF H'FFFF8000 On-chip peripheral I/O registers H'FFFFBFFF H'FFFFC000 Reserved area H'FFFFCFFF H'FFFFD000 On-chip RAM ...
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Mode 0 H'00000000 CS0 area H'0003FFFF H'00040000 Reserved area H'FFFF7FFF H'FFFF8000 On-chip peripheral I/O registers H'FFFFBFFF H'FFFFC000 Reserved area H'FFFFDFFF H'FFFFE000 On-chip RAM H'FFFFFFFF Figure 3.2 The Address Map for the Operating Modes of SH7049 Mask ROM Version ROM: 128 ...
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Initial State of This LSI In this LSI, some on-chip modules are set to module standby state as its initial state for power down. Therefore, to operate those modules necessary to clear module standby state. For details, ...
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Section 4 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and peripheral clock (Pφ) to generate the internal clock (φ/2 to φ/8192, Pφ/2 to Pφ/1024). The CPG consists of an ...
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Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.1.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed ...
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External Clock Input Method Figure 4.4 shows an example of an external clock input connection. In this case, make the external clock high level to stop it in standby mode. During operation, make the external input clock frequency 4 ...
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Function for Detecting the Oscillator Halt This CPG can detect a clock halt and automatically cause the timer pins to become high- impedance when any system abnormality causes the oscillator to halt. That is, when a change of EXTAL ...
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Usage Notes 4.3.1 Note on Crystal Resonator A sufficient evaluation at the user’s site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to the crystal resonator are ...
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A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Place oscillation stabilization capacitor C1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Separate PLLVcL and PLLVss circuit ...
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Section 5 Exception Processing 5.1 Overview 5.1.1 Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exception processing sources ...
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Exception Processing Operations The exception processing sources are detected and the processing starts according to the timing shown in table 5.2. Table 5.2 Timing for Exception Source Detection and Start of Exception Processing Exception Source Reset Power-on reset Manual ...
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Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the ...
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Exception Sources Interrupts IRQ0 IRQ1 IRQ2 IRQ3 Reserved by system Reserved by system Reserved by system Reserved by system 2 On-chip peripheral module * Notes: 1. For flash version only 2. The vector numbers and vector table address offsets for ...
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Resets 5.2.1 Types of Reset Resets have the highest priority of any exception source. There are two types of resets: manual resets and power-on resets. As table 5.5 shows, both types of resets initialize the internal status of the ...
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Power-On Reset by WDT: When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode, and the WDT’s TCNT overflows, the LSI becomes power- on reset state. The pin function ...
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Address Errors 5.3.1 The Cause of Address Error Exception Address errors occur when instructions are fetched or data is read or written, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Bus Master ...
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Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends, the current instruction finishes, and then address error exception processing starts. The CPU operates as follows: 1. The status register ...
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Interrupts 5.4.1 Interrupt Sources Table 5.7 shows the sources that start the interrupt exception processing. They are NMI, user breaks, H-UDI, IRQ and on-chip peripheral modules. Table 5.7 Interrupt Sources Type NMI User break H-UDI IRQ On-chip peripheral module ...
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Interrupt Priority Level The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception processing according to the results. The priority of interrupts is expressed as ...
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Exceptions Triggered by Instructions 5.5.1 Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Types of Exceptions Triggered by Instructions ...
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Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is called “instruction placed in a delay slot”. When the instruction placed in the delay slot is an undefined code, illegal slot exception processing starts after the ...
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Cases when Exception Sources Are Not Accepted When an address error or interrupt is generated directly after a delayed branch instruction or interrupt-disabled instruction sometimes not accepted immediately but stored instead, as shown in table 5.10. In ...
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Stack Status after Exception Processing Ends The status of the stack after exception processing ends is shown in table 5.11. Table 5.11 Stack Status after Exception Processing Ends Types Address error Trap instruction General illegal instruction Interrupt Illegal slot ...
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Usage Notes 5.8.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four not, an address error will occur when the stack is accessed during exception processing. 5.8.2 ...
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Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. 6.1 Features • 16 levels of interrupt priority • NMI noise canceler function • Occurrence of interrupt can ...
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IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 (Interrupt request) UBC (Interrupt request) H-UDI (Interrupt request) DTC (Interrupt request) MTU (Interrupt request) CMT (Interrupt request) MMT (Interrupt request) A/D (Interrupt request) SCI (Interrupt request) WDT (Interrupt request) HCAN2 (Interrupt request) I/O ICR1 ...
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Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Non-maskable interrupt input pin Interrupt request input pins Interrupt request output pin 6.3 Register Descriptions The interrupt controller has the following registers. For details on ...
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Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that sets the input signal detection mode of the external interrupt input pins NMI and IRQ0 to IRQ3 and indicates the input signal level at the NMI pin. Initial ...
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Initial Bit Bit Name Value 5 IRQ2S 0 4 IRQ3S 0 All 0 6.3.2 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins ...
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Initial Bit Bit Name Value 13 IRQ1ES1 0 12 IRQ1ES0 0 11 IRQ2ES1 0 10 IRQ2ES0 0 9 IRQ3ES1 0 8 IRQ3ES0 0 All 0 Rev. 2.00, 09/04, page 78 of 720 R/W Description R/W This ...
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IRQ Status Register (ISR) ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by ...
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Interrupt Priority Registers (IPRA, IPRD to IPRI, IPRK) Interrupt priority registers are nine 16-bit readable/writable registers that set priority levels from for interrupts except NMI. For the correspondence between interrupt request ...
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Initial Bit Bit Name Value 7 IPR7 0 6 IPR6 0 5 IPR5 0 4 IPR4 0 3 IPR3 0 2 IPR2 0 1 IPR1 0 0 IPR0 0 Note: Name in the tables above is represented by a general ...
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Interrupt Sources 6.4.1 External Interrupts There are five types of interrupt sources: NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and ...
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Level IRQ pins detection Edge detection RESIRQn (Acceptance of IRQn interrupt/DTC transfer end/ writing 0 after reading IRQnF = 1) Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control 6.4.2 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are ...
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Interrupt Exception Processing Vectors Table Table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are ...
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Table 6.2 Interrupt Exception Processing Vectors and Priorities Interrupt Source Name External pin NMI User break H-UDI Reserved by system Interrupts IRQ0 IRQ1 IRQ2 IRQ3 Reserved by system Reserved by system Reserved by system Reserved by system Reserved ...
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Interrupt Source Name MTU channel 3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 MTU channel 4 TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 Reserved by system A/D ADI0 ADI1 DTC SWDTEND CMT CMI0 CMI1 Watchdog ITI timer Reserved by system I/O (MTU) ...
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Interrupt Source Name SCI channel 4 ERI_4 RXI_4 TXI_4 TEI_4 MMT TGIM TGIN Reserved by system Reserved by system I/O(MMT) MMTPOE Reserved by system HCAN2 ERS1 OVR1 RM1 SLE1 Reserved by system Vector Table Vector Starting ...
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Interrupt Operation 6.6.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6 flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects ...
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Program execution state No Interrupt? Yes No NMI? Yes User break? Yes *1 IRQOUT = low Save SR to stack Save PC to stack Copy accept-interrupt level IRQOUT = high Read exception vector table Branch ...
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Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address 4n–8 4n–4 4n Notes: *1 PC: Start address of the next instruction (return destination instruction) after the executing instruction *2 Always make sure that ...
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Interrupt Response Time Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. ...
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IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address ...
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Data Transfer with Interrupt Request Signals The following data transfers can be done using interrupt request signals: • Activate DTC only, CPU interrupts according to DTC settings The INTC masks CPU interrupts when the corresponding DTE bit is 1. ...
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Handling Interrupt Request Signals as Source for DTC Activating, but Not CPU Interrupt 1. For DTC, set the corresponding DTE bits to 1 and clear the DISEL bits Activating sources are applied to the DTC when ...
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Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that make program debugging easier. By setting break conditions in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated ...
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Figure 7.1 shows a block diagram of the UBC. Module bus UBBR UBCR Break condition UBARH, UBARL: User break address registers H, L UBAMRH, UBAMRL: User break address mask registers H, L UBBR: User break bus cycle register UBCR: User ...
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Register Descriptions The UBC has the following registers. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. • User break address register H (UBARH) • User break address register L ...
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User Break Address Mask Register (UBAMR) The user break address mask register (UBAMR) consists of two registers: user break address mask register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit readable/writable registers. UBAMRH specifies ...
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Initial Bit Bit Name Value 5 ID1 0 4 ID0 0 3 RW1 0 2 RW0 0 1 SZ1 0 0 SZ0 0 Note: When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are * ...
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User Break Control Register (UBCR) The user break control register (UBCR 16-bit readable/writable register that (1) enables or disables user break interrupts and (2) sets the pulse width of the UBCTRG signal output in the event of ...
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Operation 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break interrupt exception processing is described below: 1. The user break addresses are set in the user break address register (UBAR), the ...
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UBARH/UBARL Internal address bits 31–0 CP1 CPU cycle DTC cycle ID1 Instruction fetch Data access RW1 Read cycle Write cycle SZ1 Byte size Word size Longword size Figure 7.2 Break Condition Determination Method Rev. 2.00, 09/04, page 102 of 720 ...
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Break on On-Chip Memory Instruction Fetch Cycle Data in on-chip memory (on-chip ROM and/or RAM) is always accessed as 32-bits data in one bus cycle. Therefore, two instructions can be retrieved in one bus cycle when fetching instructions from ...
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Examples of Use Break on CPU Instruction Fetch Cycle 1. Register settings: UBARH = H'0000 UBARL = H'0404 UBBR = H'0054 UBCR = H'0000 Conditions set: Address: H'00000404 Bus cycle: CPU, instruction fetch, read (operand size is not included ...
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Break on CPU Data Access Cycle 1. Register settings: UBARH = H'0012 UBARL = H'3456 UBBR = H'006A UBCR = H'0000 Conditions set: Address: H'00123456 Bus cycle: CPU, data access, write, word Interrupt requests enabled A user break interrupt occurs ...
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Usage Notes 7.5.1 Simultaneous Fetching of Two Instructions Two instructions may be simultaneously fetched in instruction fetch operation. Once a break condition is set on the latter of these two instructions, a user break interrupt will occur before the ...
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Contention between User Break and Exception Processing If a user break is set for the fetch of a particular instruction, and exception processing with higher priority than a user break is in contention and is accepted in the decode ...
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Module Standby Mode Setting The UBC can set the module disable/enable by using the module standby control register 2 (MSTCR2). By releasing the module standby mode, register access becomes to be enabled. By setting the MSTP0 bit of MSTCR2 ...
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Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. The DTC’s register information ...
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On-chip ROM On-chip RAM On-chip peripheral module CPU interrupt request source clear control Interrupt request External memory External device (memory- mapped) Notes DTMR: DTC mode register DTCR: DTC transfer count register DTSAR: DTC source address register DTDAR: DTC destination address ...
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Register Descriptions DTC has the following registers. • DTC mode register (DTMR) • DTC source address register (DTSAR) • DTC destination address register (DTDAR) • DTC initial address register (DTIAR) • DTC transfer count register A (DTCRA) • DTC ...
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DTC Mode Register (DTMR) DTMR is a 16-bit register that selects the DTC operating mode. Initial Bit Bit Name Value 15 SM1 Undefined 14 SM0 Undefined 13 DM1 Undefined 12 DM0 Undefined 11 MD1 Undefined 10 MD0 Undefined 9 ...
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Initial Bit Bit Name Value 7 DTS Undefined 6 CHNE Undefined 5 DISEL Undefined 4 NMIM Undefined Undefined [Legend] X: Don’t care R/W Description DTC Transfer Mode Select Specifies whether the source or the destination ...
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DTC Source Address Register (DTSAR) The DTC source address register (DTSAR 32-bit register that specifies the DTC transfer source address. Specify an even address in case the transfer size is word; specify a multiple-of- four address in ...
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DTC Enable Registers (DTER) DTER which is comprised of seven registers, DTEA to DTEF register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTE bits is shown in table 8.1. Initial Bit Bit ...
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DTC Control/Status Register (DTCSR) The DTCSR is a 16-bit readable/writable register that disables/enables DTC activation by software and sets the DTC vector addresses for software activation. It also indicates the DTC transfer status. Initial Bit Bit Name Value 15 ...
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Initial Bit Bit Name Value 7 DTVEC7 0 6 DTVEC6 0 5 DTVEC5 0 4 DTVEC4 0 3 DTVEC3 0 2 DTVEC2 0 1 DTVEC1 0 0 DTVEC0 0 Notes: 1. For the NMIF and AE bits, only a 0 ...
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Operation 8.3.1 Activation Sources The DTC operates when activated by an interrupt write to DTCSR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTER bit. At ...
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Memory space Register information DTCRA start address DTSAR DTDAR Normal mode Figure 8.3 DTC Register Information Allocation in Memory Space Figure 8.4 shows the correspondence between DTC vector addresses and register information allocation. For each DTC activating source there are ...
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Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTEs Activating Source Activating Generator Source MTU (CH4) TGI4A TGI4B TGI4C TGI4D TGI4V MTU (CH3) TGI3A TGI3B TGI3C TGI3D MTU (CH2) TGI2A TGI2B MTU (CH1) TGI1A TGI1B MTU (CH0) TGI0A TGI0B ...
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Activating Source Activating Generator Source Reserved A/D converter ADI1 (CH1) Reserved SCI2 RXI_2 TXI_2 SCI3 RXI_3 TXI_3 SCI4 RXI_4 TXI_4 MMT TGN TGM Reserved HCAN2 RM1 Reserved Software Write to DTCSR Note: * External memory, memory-mapped ...
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DTMR, DTCR, DTIAR, DTSAR, DTDAR NMIF = Transfer request DTC vector read Transfer information read DTCRA = DTCRA – 1 (normal/block transfer mode) DTCRAL = DTCRAL – 1 (repeat mode) Transfer (1 transfer unit) DTSAR, DTDAR update ...
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Normal Mode: Performs the transfer of one byte, one word, or one longword for each activation. The total transfer count 65536. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8.2 ...
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Repeat Mode: Performs the transfer of one byte, one word, or one longword for each activation. Either the transfer source or transfer destination is designated as the repeat area. Table 8.3 lists the register information in repeat mode. From 1 ...
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Block Transfer Mode: Performs the transfer of one block for each one activation. Either the transfer source or transfer destination is designated as the block area. The block length is specified between 1 and 65536. When the transfer of one ...
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Chain Transfer: Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in a single activation source. DTSAR, DTDAR, DTMR, DTCRA, and DTCRB can be set independently. Figure 8.9 shows the chain transfer. When ...
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Interrupt Source An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers data transfer for which the DISEL bit was set the case of interrupt activation, ...
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DTC Execution State Counts Table 8.5 shows the execution state for one DTC data transfer. Furthermore, Table 8.6 shows the state counts needed for execution state. Table 8.5 Execution State of DTC Vector Read Mode I Normal 1 Repeat ...
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Procedures for Using DTC 8.4.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR register information in memory space. 2. Establish the register ...
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DTC Use Example The following is a DTC use example of a 128-byte data reception by the SCI: 1. The settings are: DTMR source address fixed (SM1 = SM0 = 0), destination address incremented (DM1 = 1, DM0 = ...
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Cautions on Use 8.5.1 Prohibition against DTC Register Access by DTC DTC register access by the DTC is prohibited. 8.5.2 Module Standby Mode Setting DTC operation can be disabled or enabled using the module standby control register. The initial ...
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Section 9 Bus State Controller (BSC) The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM and ROM to be linked directly to the chip without external ...
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On-chip memory control unit Wait control WAIT Area control CS0 RD Memory control WRL WCR1: Wait control register 1 BCR1: Bus control register 1 BCR2: Bus control register 2 RAMER: RAM emulation register Rev. 2.00, 09/04, page 134 of 720 ...
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Input/Output Pin Table 9.1 shows the bus state controller pin configuration. Table 9.1 Pin Configuration Name Abbr. Address bus A17 to A0 Data bus CS0 Chip select RD Read WRL Lower write WAIT Wait BREQ Bus ...
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Address Map Figure 9.2 shows the address format used by this LSI. A31 to A24 A23, A22 Space selection: Not output externally; used to select the type of space On-chip ROM space or CS0 space when 00000000 (H'00) Reserved ...
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Table 9.2 Address Map • On-chip ROM enabled mode Address H'0000 0000 to H'0000 FFFF H'0001 0000 to H'0001 FFFF H'0002 0000 to H'0003 FFFF H'0004 0000 to H'001F FFFF H'0020 0000 to H'0023 FFFF H'0024 0000 to H'FFFF 7FFF ...
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Description of Registers 9.5.1 Bus Control Register 1 (BCR1) BCR1 is a 16-bit readable/writable register that enables access to the MMT and MTU control registers and specifies the bus size of the CS0 space. The AOSZ bit of BCR1 ...
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Bus Control Register 2 (BCR2) BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS0 signal assert extension of each CS0 space. Initial Bit Bit Name Value All 1 9 ...
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Wait Control Register 1 (WCR1) WCR1 is a 16-bit readable/writable register that specifies the number of wait cycles for CS0 space. Initial Bit Bit Name Value All 1 3 W03 1 2 W02 1 1 ...
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Accessing External Space A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct connections. 9.6.1 Basic Timing External access bus cycles are performed in 2 states. Figure 9.3 shows the basic timing ...
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Wait State Control The number of wait states inserted into external space access states can be controlled using the WCR1 settings. The specified number of T shown in figure 9.4. Address Read WRL Write Figure 9.4 Wait State Timing ...
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When the wait is specified by software using WCR1, the wait input WAIT signal from outside is sampled. Figure 9.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise ...
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CS Assert Period Extension 9.6.3 Idle cycles can be inserted to prevent extension of the RD or WRL signal assert period beyond the length of the CS0 signal assert period by setting the SW0 bit of BCR2. This allows for ...
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Waits between Access Cycles When a read from a slow device is completed, data buffers may not go off in time, causing conflict with the next access data. If there is a data conflict during memory access, the problem ...
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Bus Arbitration This LSI has a bus arbitration function that, when a bus release request is received from an external device, releases the bus to that device. It also has three internal bus masters, the CPU, DTC, and AUD ...
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This LSI BREQ accepted Strobe pin: high-level output Address, data, strobe pin: high impedance Bus release response Bus mastership release status Figure 9.8 Bus Mastership Release Procedure 9.9 Memory Connection Example Figure 9.9 Example of 8-bit Data Bus Width ROM ...
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On-chip Peripheral I/O Register Access On-chip peripheral I/O registers are accessed from the bus state controller, as shown in Table 9.3. Table 9.3 On-chip Peripheral I/O Register Access On-chip Peripheral MTU, Module SCI POE INTC Connected 8bit 16bit 16bit ...
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Section 10 Multi-Function Timer Pulse Unit (MTU) This LSI has an on-chip multi-function timer pulse unit (MTU) that comprises five 16-bit timer channels. The block diagram is shown in figure 10.1. 10.1 Features • Maximum 16-pulse input/output • Selection of ...
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Table 10.1 MTU Functions Item Channel 0 Count clock Pφ/1 Pφ/4 Pφ/16 Pφ/64 TCLKA TCLKB TCLKC TCLKD General registers TGRA_0 TGRB_0 General registers/ TGRC_0 buffer registers TGRD_0 I/O pins TIOC0A TIOC0B TIOC0C TIOC0D Counter clear TGR function compare match or ...
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Item Channel 0 DTC activation TGR compare match or input capture A/D converter start TGRA_0 trigger compare match or input capture Interrupt sources 5 sources • Compare match or input capture 0A • Compare match or input capture 0B • ...
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Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D Clock input Internal clock: Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 External clock: TCLKA TCLKB TCLKC TCLKD Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: ...
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Input/Output Pins Table 10.2 MTU Pins Channel Symbol I/O Common TCLKA Input TCLKB Input TCLKC Input TCLKD Input 0 TIOC0A I/O TIOC0B I/O TIOC0C I/O TIOC0D I/O 1 TIOC1A I/O TIOC1B I/O 2 TIOC2A I/O TIOC2B I/O 3 TIOC3A ...
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Register Descriptions The MTU has the following registers. For details on register addresses and register states during each process, refer to appendix A, Internal I/O Register. To distinguish registers in each channel, an underscore and the channel number are ...
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Timer interrupt enable register_3 (TIER_3) • Timer status register_3 (TSR_3) • Timer counter_3 (TCNT_3) • Timer general register A_3 (TGRA_3) • Timer general register B_3 (TGRB_3) • Timer general register C_3 (TGRC_3) • Timer general register D_3 (TGRD_3) • ...
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Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR register settings ...
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Table 10.3 CCLR0 to CCLR2 (channels 0, 3, and 4) Bit 7 Bit 6 Channel CCLR2 CCLR1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to ...
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Table 10.5 TPSC0 to TPSC2 (channel 0) Bit 2 Bit 1 Channel TPSC2 TPSC1 Table 10.6 TPSC0 to TPSC2 (channel 1) Bit 2 Bit 1 Channel TPSC2 TPSC1 ...