HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 554

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.8.4
Input Level Detection: When the input condition set in ICSR2 occurs on any one of the POE
pins, the MMT output pins go to the high-impedance state.
• Pins placed in the high-impedance state (the MMT's output pins)
Note: These pins are in the high-impedance state only when each pin is used as the general
1. Falling edge detection
2. Low level detection
Exiting High-Impedance State: The MMT output pins that have entered the high-impedance
state by the input level detection are released from this state by restoring them to their initial states
by means of a power-on reset, or by clearing all the POE flags in ICSR2 (POE4F to POE6F: bits
12 to 14).
Rev. 2.00, 09/04, page 512 of 720
Pφ
Sampling clock
POE input
PUOA
All low-level samples
At least one high-level
sample
Note: The other MMT output pins also go to the high-impedance state at the same timing.
The six pins PWOB, PWOA, PVOB, PVOA, PUOB, PUOA in the motor management timer
(MMT) are placed in the high-impedance state.
When a transition from high- to low-level input occurs on a POE pin
Figure 16.19 shows the low level detection operation. Low level sampling is performed 16
times in succession using the sampling clock set in ICSR2. The input is not accepted if a high
level is detected even once among these samples.
The timing of entry of the MMT's output pins into the high-impedance state from the sampling
clock is the same for falling edge detection and low level detection.
input/output function or MMT output pin.
Operation
Figure 16.19 Low Level Detection Operation
[1]
[1]
128 clocks
8, 16, or
[2]
[2]
[3]
[16] Flag set (POE accepted)
[13]
High-impedance state
Flag not set