HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 270

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2. Register Operation
Rev. 2.00, 09/04, page 228 of 720
In complementary PWM mode, nine registers are used, comprising compare registers, buffer
registers, and temporary registers. Figure 10.35 shows an example of complementary PWM
mode operation.
The registers which are constantly compared with the counters to perform PWM output are
TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in
bits OLSN and OLSP in the timer output control register (TOCR) is output.
The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4.
Between a buffer register and compare register there is a temporary register. The temporary
registers cannot be accessed by the CPU.
Data in a compare register is changed by writing the new data to the corresponding buffer
register. The buffer registers can be read or written at any time.
The data written to a buffer register is constantly transferred to the temporary register in the Ta
interval. Data is not transferred to the temporary register in the Tb interval. Data written to a
buffer register in this interval is transferred to the temporary register at the end of the Tb
interval.
The value transferred to a temporary register is transferred to the compare register when
TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when
counting down. The timing for transfer from the temporary register to the compare register can
be selected with bits MD3–MD0 in the timer mode register (TMDR). Figure 10.35 shows an
example in which the mode is selected in which the change is made in the trough.
In the tb interval (tb1 in Figure 10.35) in which data transfer to the temporary register is not
performed, the temporary register has the same function as the compare register, and is
compared with the counter. In this interval, therefore, there are two compare match registers
for one-phase output, with the compare register containing the pre-change data, and the
temporary register containing the new data. In this interval, the three countersTCNT_3,
TCNT_4, and TCNTSand two registerscompare register and temporary registerare
compared, and PWM output controlled accordingly.