HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 233

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.3.12 Timer Gate Control Register (TGCR)
TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode.
These register settings are ineffective for anything other than complementary PWM mode/reset-
synchronized PWM mode.
Bit
7
6
5
4
3
Bit Name

BDC
N
P
FB
Initial
value
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
This bit is always read as 1. Only 1 should be written to this
bit.
Brushless DC Motor
This bit selects whether to make the functions of this
register (TGCR) effective or ineffective.
0: Ordinary output
1: Functions of this register are made effective
Reverse Phase Output (N) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while the
reverse pins (TIOC3D, TIOC4C, and TIOC4D) are on-
output.
0: Level output
1: Reset synchronized PWM/complementary PWM output
Positive Phase Output (P) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while the
positive pin (TIOC3B, TIOC4A, and TIOC4B) are on-output.
0: Level output
1: Reset synchronized PWM/complementary PWM output
External Feedback Signal Enable
This bit selects whether the switching of the output of the
positive/reverse phase is carried out automatically with the
MTU/channel 0 TGRA, TGRB, TGRC input capture signals
or by writing 0 or 1 to bits 2 to 0 in TGCR.
0: Output switching is carried out by external input (Input
1: Output switching is carried out by software (TGCR's UF,
sources are channel 0 TGRA, TGRB, TGRC input
capture signal)
VF, WF settings).
Rev. 2.00, 09/04, page 191 of 720