DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 966

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 6.00 Sep. 24, 2009 Page 918 of 928
REJ09B0099-0600
Item
13.3.7 Serial Status
Register (SSR)
•
20.1.2 Operating Mode
Table 20.1 MD Pin
Setting and Operating
Mode
20.4.3 User Boot Mode
Smart Card Interface
Mode (When SMIF in
SCMR Is 1)
Page
415
416
669
716
717
Revision (See Manual for Details)
Notes:
3. To clear the flag by using the CPU, write 0 to the flag and
Table amended and note added
Notes:
3. In case of On-chip ROM valid mode, User program mode
Description amended
The area that can be executed in the steps of the user
procedure program (on-chip RAM and user MAT
in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
Description amended
The area that can be executed in the steps of the user
procedure program (on-chip RAM and user MAT
in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
Bit
3
Pin
RES
MD0*
MD1
MD2
then read it once again.
and Boot mode, when the MD0 pin sets to 0, the mode will
be Expanded mode, otherwise, when the pin sets to 1, the
mode will be Single chip mode. However, in case of User
boot mode, there is no Expanded mode.
3
PER
Reset
state
Bit Name
0
0/1
0/1
0/1
On-chip ROM
valid mode*
Initial
Value
0
0/1
1
1
1
1
R/W
R/(W)*
User program
mode*
1
Description
Parity Error
Indicates that a parity error occurred during reception
using parity addition in asynchronous mode, causing
abnormal termination.
[Setting condition]
•
If a parity error occurs, the receive data is transferred to
RDR but the RDRF flag is not set. Also, subsequent
serial reception cannot be continued while the PER flag is
set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing condition]
•
The PER flag is not affected and retains its previous state
when the RE bit in SCR is cleared to 0.
0/1
2
1
1
1
When a parity error is detected during reception
When 0 is written to PER after reading PER = 1*
User boot
mode
1
1
0
0
Boot
0/1
mode
1
1
0
) is shown
) is shown
Programmer
mode
1
0
0
0
3