DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 748

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory
(1)
When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communica-
tion data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format
is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the
host by means of the measured low period and transmits the bit adjustment end sign (1 byte of
H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received
normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot
mode is initiated again (reset) and the operation described above must be executed. The bit rate
between the host and this LSI is not matched by the bit rate of transmission by the host and system
clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be
set to 9,600 bps or 19,200 bps.
The system clock frequency, which can automatically adjust the transfer bit rate of the host and
the bit rate of this LSI, is shown in table 20.7. Boot mode must be initiated in the range of this
system clock.
Table 20.7 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI
(2)
The overview of the state transition diagram after boot mode is initiated is shown in figure 20.8.
1. Bit rate adjustment
2. Waiting for inquiry set command
3. Automatic erasure of all user MAT and user boot MAT
Rev. 6.00 Sep. 24, 2009 Page 700 of 928
REJ09B0099-0600
Bit Rate of Host
9,600 bps
19,200 bps
After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host.
For inquiries about user-MAT size and configuration, MAT start address, and support state,
the required information is transmitted to the host.
SCI Interface Setting by Host
State Transition Diagram
Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI
Start
bit
System Clock Frequency
10 to 26 MHz
16 to 26 MHz
D0
Measure low period (9 bits) (data is H'00)
D1
D2
D3
D4
D5
D6
D7
High period of
at least 1 bit
Stop bit