DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 603

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.1.4
Figure 17.5 shows the bit format (conceptual diagram) configuring the IEBus communications
frame.
Each period of bit format for use of active high signals is described below.
• Preparation period: first logic 1 period (high level)
• Synchronous period: subsequent logic 0 period (low level)
• Data period: period indicating bit value (logic 1: high level, logic 0: low level)
• Halt period: last logic 1 cycle (high level)
For use of active low signals, levels are reversed from the active high signals.
The synchronous and data periods have approximately the same length.
The IEBus is synchronized bit by bit. The specifications for the time of all bits and the periods
allocated to the bits differ depending on the type of transfer bits and the unit (master or slave unit).
Bit Format
Note that the LCK flag in IEFLG can be used to check whether the unit is
locked/unlocked.
Logic 1
Logic 0
Figure 17.5 IEBus Bit Format (Conceptual Diagram)
Active low: Logic 1 = low level and logic 0 = high level
Active high: Logic 1 = high level and logic 0 = low level
Preparation
period
Synchronous
period
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
period
Rev. 6.00 Sep. 24, 2009 Page 555 of 928
Data
period
Halt
REJ09B0099-0600