DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 647

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4.4
This section shows an example of performing a slave transmission using the DTC after slave
reception.
(1)
(a) Setting the IEBus Control Register (IECTR)
(b) Setting the IEBus Master Unit Address Registers 1 and 2 (IEAR1 and IEAR2)
(c) Setting the IEBus Transmit Message Length Register (IETBFL)
(d) Setting the IEBus Transmit/Runaway Interrupt Enable Register (IEIET)
The above registers can be specified in any order. (The register specification order does not affect
the IEB operation.)
(2)
1. Set the start address of the RAM which stores the register information necessary for the DTC
2. Set the following data from the start address of the RAM.
3. Set bit DTCEG5 in the DTC enabler register G (DTCERG), and enable the TxRDY interrupt
Enable the IEBus pins, select the signal polarity, and select a clock supplied to the IEB. Clear
the LUEE bit to 0 because transfer by the DTC is performed.
Specify the master unit address and specify the communications mode in IEAR1. Compare
with the slave address in the communications frame and receive the frame if matched.
Specify the message length bits.
Enable the TxRDY (IETxI), TxS, and TxE (IETSI) interrupts.
transfer in the vector address (H'000004D4) to be accessed a DTC transfer request is
generated.
⎯ Transfer source address (SAR): Start address of the RAM which stores data to be
⎯ Transfer destination address (DAR): Address (H'FFF808) of the IEBus transmit buffer
⎯ Transfer count (CRA): The same value as IETBFL
(IETxI).
Because the TxRDY flag is retained after reset, the DTC transfer is executed when the IETxI is
enabled and the first data field data is written to IETBR. The DTC negates the TxRDY flag
and the DTC transfer of the first byte is completed.
IEB Initialization
DTC Initialization
transmitted from the data field.
register (IETBR)
Slave Transmission
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
Rev. 6.00 Sep. 24, 2009 Page 599 of 928
REJ09B0099-0600