DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 648

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
(3)
Figure 17.12 shows the slave transmission flow. Numbers in the following description correspond
to the numbers in Figure 17.12.
1. After the IEB and DTC have been initialized, a slave communications request command is
2. The CMX flag is cleared when the slave reception is completed, the slave communications
3. If data up to the control field has been received correctly and if the contents of the control bits
4. The slave then transmits the message length field, and the IEB loads the transmit data in the
5. Similarly, the above data field load and transmission operations are repeated.
6. The DTC completes the data transfer for the number of specified bytes when data to be
7. A TxRDY interrupt (IETxI) is issued to the CPU when the DTC transfer is completed. In this
8. After the last data transfer has been completed, a transmit normal completion (TxF) interrupt
Notes: 1. As a transmit status interrupt (IETSI), a transmit error termination (TxE) interrupt as
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REJ09B0099-0600
issued from IECMR. During slave reception, the command execution status flag (CMX) in
IEFLG is set and the slave communications request will not be issued.
command is executed, and the SRQ flag is set.
is H'3 or H'7, the transmit start detection flag (TxS) in IETSR register is set to 1. In this case,
the TxS flag is cleared in the TxS interrupt handling routine.
data field from IETBR when the ACK is received. Then the TxRDY flag is set to 1. A DTC
transfer request by IETxI is generated and the second byte data is written to the transmit
buffer.
transmitted in the last byte is written to. At this time, the DTC does not clear the TxRDY flag.
It, however, clears bit DTCEG5 in the DTC enable register G (DTCERG) not to generate more
DTC transfer request.
interrupt handling routine, the TxRDY flag can be cleared. However, since the TxRDY
interrupt will be generated again after the last byte transfer, the TxRDY flag remains set. (Note
that the LUEE bit should be cleared to 0 because an underrun error occurs to terminate the
transfer if the LUEE bit in IECTR is set to 1.) Note, however, that the TxRDY interrupt should
be disabled because the TxRDY interrupt is always generated.
occurs. In this case, the CPU clears the TxF flag and completes the normal completion
interrupt and clears the SRQ flag to 0.
Slave Transmission Flow
2. If the control bits sent from the master unit is H'0, H'4, H'5, or H'6 in slave
well as the transmit start detection (TxS) and transmit normal completion (TxF)
interrupts must be enabled. If a transmit error completion interrupt is disabled, no
interrupt is generated even if the transfer is terminated by an error.
transmission, the IEB automatically performs processing and the TxS and TxF flags are
not set.