DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 238

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
8.7
8.7.1
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. MRA sets the source address fixed (SM1 = SM0 = 0), destination address increment (DM1 =
2. Set the start address of the register information in the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the
5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in
6. When CRA becomes 0 after the 128 data transfers have been completed, the RDRF flag is
8.7.2
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the transfer destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
1. MRA sets the source address increment (SM1 = 1, SM0 = 0), destination address increment
2. Set the start address of the register information at the DTC vector address (H'04C0).
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1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can be set
to any value. MRB performs one data transfer by one interrupt (CHNE = 0, DISEL = 0). SAR
sets the RDR address in SCI, DAR sets the start address of the RAM area where the data will
be received in, and CRA sets 128 (H'0080). CRB can be set to any value.
reception complete (RXI) interrupt. Since the generation of a receive error during the SCI
reception operation will disable subsequent reception, the CPU should be enabled to accept
receive error interrupts.
SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is
transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented.
The RDRF flag is automatically cleared to 0.
held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The
interrupt handling routine will perform wrap-up processing.
(DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The
DTS bit can be set to any value. MRB performs one block transfer by one interrupt (CHNE =
0). SAR sets the transfer source address (H'1000), DAR sets the transfer destination address
(H'2000), and CRA sets 128 (H'8080). CRB sets 1 (H'0001).
Examples of Use of the DTC
Normal Mode
Software Activation