DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 554

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
Rev. 6.00 Sep. 24, 2009 Page 506 of 928
REJ09B0099-0600
No
No
No
Clear ACKBT in ICIER to 0
Clear RCVD in ICCR1 to 0
Clear TRS in ICCR1 to 0
Set ACKBT in ICIER to 1
Clear MST in ICCR1 to 0
Set RCVD in ICCR1 to 1
Clear STOP in ICSR.
Dummy-read ICDRR
2
Clear TEND in ICSR
Clear TDRE in ICSR
Read RDRF in ICSR
Read RDRF in ICSR
Read STOP in ICSR
Mater receive mode
C Bus Interface 2 (IIC2)
Write 0 to BBSY
Read ICDRR
Read ICDRR
Read ICDRR
Last receive
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
and SCP
End
- 1?
Figure 14.18 Sample Flowchart for Master Receive Mode
Yes
Yes
Yes
No
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
Notes:
Clear TEND, select master receive mode, and then clear TDRE.*
Set acknowledge to the transmit device.*
Dummy-read ICDDR.*
Wait for 1 byte to be received
Check whether it is the (last receive - 1).
Read the receive data last.
Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
Read the (final byte - 1) of receive data.
Wait for the last byte to be receive.
When receiving one byte, execute step [7] after step [1] without executing
steps [2] to [6]. The step [8] is ICDRR dummy read.
* Do not activate an interrupt during the execution of steps [1] to [3].