DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 676

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 Controller Area Network (HCAN) [H8S/2556 Group]
18.3.12 Mailbox Interrupt Mask Register (MBIMR)
MBIMR controls the enabling or disabling of individual mailbox interrupt requests.
18.3.13 Interrupt Mask Register (IMR)
IMR enables or disables requests by individual interrupt sources of IRR. The interrupt flag cannot
be masked.
Rev. 6.00 Sep. 24, 2009 Page 628 of 928
REJ09B0099-0600
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
15
14
Bit Name
MBIMR7
MBIMR6
MBIMR5
MBIMR4
MBIMR3
MBIMR2
MBIMR1
MBIMR0
MBIMR15
MBIMR14
MBIMR13
MBIMR12
MBIMR11
MBIMR10
MBIMR9
MBIMR8
Bit Name
IMR7
IMR6
Initial Value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Initial
Value
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Overload Frame Recovery Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR7) is enabled. When set to 1, OVR0 is masked.
Bus Off Interrupt Mask
When this bit is cleared to 0, ERS0 (interrupt request by
IRR6) is enabled. When set to 1, ERS0 is masked.
Description
Mailbox Interrupt Mask (MBIMRx)
When MBIMRn (n = 0 to 15) is cleared to 0, the
interrupt request in mailbox n is enabled. When set
to 1, the interrupt request is masked.
The interrupt source in a transmit mailbox is TXPR
clearing caused by transmission end or
transmission cancellation. The interrupt source in a
receive mailbox is RXPR setting on reception end.