DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 677

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
13
12
11
10
9
8
7 to 5 ⎯
4
3, 2
1
0
Bit Name
IMR5
IMR4
IMR3
IMR2
IMR1
⎯
IMR12
⎯
IMR9
IMR8
Initial
Value
1
1
1
1
1
0
All 1
1
All 1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R
R/W
R/W
Description
Error Passive Interrupt Mask
When this bit is cleared to 0, ERS0 (interrupt request by
IRR5) is enabled. When set to 1, ERS0 is masked.
Receive Overload Warning Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR4) is enabled. When set to 1, OVR0 is masked.
Transmit Overload Warning Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR3) is enabled. When set to 1, OVR0 is masked.
Remote Frame Request Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR2) is enabled. When set to 1, OVR0 is masked.
Receive Message Interrupt Mask
When this bit is cleared to 0, RM1 (interrupt request by
IRR1) is enabled. When set to 1, RMI is masked.
Reserved
This bit is always read as 0. The write value should always
be 0.
Reserved
These bits are always read as 1. The write value should
always be 1.
Bus Operation Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR12) is enabled. When set to 1, OVR0 is masked.
Reserved
These bits are always read as 1. The write value should
always be 1.
Unread Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR9) is enabled. When set to 1, OVR0 is masked.
Mailbox Empty Interrupt Mask
When this bit is cleared to 0, SLE0 (interrupt request by
IRR8) is enabled. When set to 1, SLE0 is masked.
Section 18 Controller Area Network (HCAN) [H8S/2556 Group]
Rev. 6.00 Sep. 24, 2009 Page 629 of 928
REJ09B0099-0600