DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 509

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.7.7
Data reception in Smart Card interface mode uses the same operation procedure as for normal
serial communication interface mode. Figure 13.29 illustrates the retransfer operation when the
SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SSR is
2. The RDRF bit in SSR is not set for a frame in which an error has occurred.
3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1,
Figure 13.30 shows a flowchart for reception. A sequence of receive operations can be performed
automatically by specifying the DTC to be activated with an RXI interrupt source. In a receive
operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI
request is designated beforehand as a DTC activation source, the DTC will be activated by the
RXI request, and the receive data will be transferred. The RDRF flag is cleared to 0 automatically
when the DISEL bit in DTC is 0 and the transfer counter is other than 0. When the DISEL bit in
DTC is 1, or both the DISEL bit and the transfer counter are 0, flags are not cleared although the
receive data is transferred by DTC. Consequently, give the CPU an instruction of flag clear
processing. If an error occurs in receive mode and the ORER or PER flag is set to 1, a transfer
error interrupt (ERI) request will be generated. Hence, so the error flag must be cleared to 0. In the
event of an error, the DTC is not activated and receive data is skipped. Therefore, receive data is
transferred for only the specified number of bytes in the event of an error. Even when a parity
error occurs in receive mode and the PER flag is set to 1, the data that has been received is
transferred to RDR and can be read from there.
Note: For details on receive operations in block transfer mode, see section 13.4, Operation in
automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
the receive operation is judged to have been completed normally, and the RDRF flag in SSR is
automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is
generated.
Asynchronous Mode.
Serial Data Reception (Except for Block Transfer Mode)
Section 13 Serial Communication Interface (SCI)
Rev. 6.00 Sep. 24, 2009 Page 461 of 928
REJ09B0099-0600