DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 221

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(n = A to G, and I)
8.2.8
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
Bit
7
6
5
4
3
2
1
0
Bit
7
Bit Name
DTCEn7
DTCEn6
DTCEn5
DTCEn4
DTCEn3
DTCEn2
DTCEn1
DTCEn0
Bit Name
SWDTE
DTC Vector Register (DTVECR)
Initial
Value
0
0
0
0
0
0
0
0
Initial
Value
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
DTC Activation Enable
1: Disables an interrupt for DTC activation.
0: Specifies a relevant interrupt source as a DTC
[Clearing conditions]
• When the DISEL bit in MRB is 1 and the data transfer
• When the specified number of transfers have ended
[Retaining condition]
• When the DISEL bit is 0 and the specified number of
Description
DTC Software Activation Enable
Enables or disables the DTC software activation.
0: Disables the DTC software activation.
1: Enables the DTC software activation.
[Clearing conditions]
• When the DISEL bit is 0 and the specified number of
• When 0 is written after a software-activated data
[Retaining conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• When the software-activated data transfer is in process
has ended
transfers have not been completed
transfers have not ended
transfer end interrupt (SWDTEND) request has been
sent to the CPU
activation source.
Rev. 6.00 Sep. 24, 2009 Page 173 of 928
Section 8 Data Transfer Controller (DTC)
REJ09B0099-0600