DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 778

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory
Figure 20.18 shows an example of an overlap on block area EB0 of the flash memory.
Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of
user MAT bank 0. The area is selected by the setting of the RAM2 to RAM0 bits in the RAMER.
1. To overlap a part of the RAM on area EB0, to allow real-time programming of the data for this
2. Real-time programming is carried out using the overlapped area of RAM.
In programming or erasing the user MAT, it is necessary to run a program that implements a series
of procedural steps, including the downloading of an on-chip program. In this process, the overlaid
RAM area and the area where the on-chip program is to be downloaded overlap. Therefore, the
data that is to be programmed must be saved beforehand in an area that is not used by the system.
Figure 20.19 shows an example of programming of the data, after emulation has been completed,
to the EB0 area in the user MAT.
Rev. 6.00 Sep. 24, 2009 Page 730 of 928
REJ09B0099-0600
area, set the RAMS bit in RAMER to 1, and each of the RAM2 to RAM0 bits to 0.
Note:
H'7FFFF*
H'00000
H'01000
H'02000
H'03000
H'04000
H'05000
H'06000
H'07000
H'08000
The H8S/2551 and H8S/2505 flash memory user MATs are allocated address
H'00000 to H'5FFFF and divided into EB0 to EB13 erasure blocks.
Figure 20.18 Example of a RAM-Overlap Operation
Flash memory
EB8 to EB15*
(user MAT)
EB0
EB1
EB2
EB3
EB4
EB5
EB6
EB7
This area is accessible as both a RAM
area and as a flash memory area.
On-chip RAM
H'FF7000
H'FFD000
H'FFDFFF
H'FFEFBF