DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 593

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
The master address field is a field for transmitting the unit address (master address) to other units.
The master address field is comprised of master address bits and a parity bit.
The master address has 12 bits and are output MSB first.
When more than one unit starts transfer of the broadcast bit having the same value at the same
timing, arbitration is decided by the master address field.
In the master address field, self-output data and data on the bus are compared for every one-bit
transfer. If the self-output master address and data on the bus are different, the unit that loses
arbitration, stops transfer, and enters the receive state.
Since the IEBus is configured with wired AND, a unit having the smallest master address of the
units in arbitration (arbitration master) wins in arbitration.
Finally, only a single unit remains in the transfer state as a master unit after outputting 12-bit
master address.
Next, this master unit outputs a parity bit*, defines the master address to other units, and then
enters the slave address field output state.
Note: Since even parity is used, when the number of one bits in the master address is odd, the
(3)
The slave address field is a field to transmit an address (slave address) of a unit (slave unit) to
which a master transmit data. The slave address field is comprised of slave address bits, a parity
bit, and an acknowledge bit.
The slave address has 12 bits and is output MSB first. The parity bit is output after the 12-bit slave
address is transmitted in order to avoid receiving the slave address accidentally. The master unit
then detects the acknowledgement from the slave unit in order to confirm that the slave unit exists
on the bus. When the acknowledgement is detected, the master unit enters the control field output
state. However, the master unit enters the control field output state without detecting the
acknowledgement in broadcast communications.
When more than one unit starts transfer of communications frame at the same timing,
broadcast communications has priority over normal communications, and arbitration occurs.
Master Address Field
Slave Address Field
parity bit is 1.
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
Rev. 6.00 Sep. 24, 2009 Page 545 of 928
REJ09B0099-0600