AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 7

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 3-1.
8549A–CAP–10/08
Signal Name
TXDx
RXDx
RTSx
CTSx
TCLKx
TIOAx
TIOBx
SPIx_MISO
SPIx_MOSI
SPIx_SPCK
SPIx_NPCS0
SPIx_NPCS1 - SPIx_NPCS3
DDM
DDP
FPP_IRQ_ENC0 -
FPP_IRQ_ENC3
FPP6_IRQ
FPP7_IRQ
FPP6_TX_BFFR_EMPTY
FPP6_RX_BFFR_FULL
FPP6_CHNL_TX_END
FPP6_CHNL_RX_END
FPP6_TX_RDY
FPP6_RX_RDY
FPP6_TX_SIZE0 -
FPP6_TX_SIZE1
Signal Description by Peripheral (Continued)
Function
USARTx Transmit Data
USARTx Receive Data
USARTx Request To Send
USARTx Clear To Send
TC Channel x External Clock Input
TC Channel x I/O Line A
TC Channel x I/O Line B
Master In Slave Out
Master Out Slave In
SPI Serial Clock
SPI Peripheral Chip Select 0
SPI Peripheral Chip Select
USB Device Port Data -
USB Device Port Data +
FPGA Peripheral encoded interrupt
requests for FPP0 thru FPP5 and FPP8
thru FPP13
FPP6 Interrupt Request
FPP7 Interrupt Request
FPP6 Transmit Buffer Empty flag
FPP6 Receive Buffer Full flag
FPP6 Channel Transmit End
FPP6 Channel Receive End
FPP6 Transmit Ready
FPP6 Receive Ready
FPP6 Transfer Size
Serial Peripheral Interface - SPI
FPGA Interface- FPIF
Timer/Counter - TC
USB Device Port
Analog
Analog
Output
Output
Type
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Active
Level
High
High
High
High
High
High
High
High
High
Low
Low
Comments
access via PIOA
access via PIOA
access via PIOA
access via PIOA
access via PIOA
access via PIOA
access via PIOA
access via PIOA
access via PIOA
access via PIOA
access via PIOA
access via PIOA
access via PIOB/ mapped to
MPIO00 thru MPIO03
access via PIOB/ mapped to
MPIO04
access via PIOB/ mapped to
MPIO05
access via PIOB/ mapped to
MPIO06
access via PIOB/ mapped to
MPIO07
access via PIOB/ mapped to
MPIO08
access via PIOB/ mapped to
MPIO09
access via PIOB/ mapped to
MPIO10
access via PIOB/ mapped to
MPIO11
access via PIOB/ mapped to
MPIO12 thru MPIO13
AT91CAP7E
7