AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 437

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 31-6. Data IN Transfer for Non Ping-pong Endpoint
Using Endpoints With Ping-pong Attribute
Figure 31-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints
8549A–CAP–10/08
USB Bus Packets
TXPKTRDY Flag
(UDP_CSRx)
TXCOMP Flag
(UDP_CSRx)
FIFO (DPR)
Content
Set by the firmware
Data IN
PID
Microcontroller
1 st Data Payload
2 nd Data Payload
3 rd Data Payload
?Data IN 1
Prevous Data IN TX
Interrupt Pending
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This
also allows handling the maximum bandwidth defined in the USB specification during bulk trans-
fer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must
prepare the next data payload to be sent while the current one is being sent by the USB device.
Thus two banks of memory are used. While one is available for the microcontroller, the other
one is locked by the USB device.
When using a ping-pong endpoint, the following procedures are required to perform Data IN
transactions:
Cleared by Hw
Data IN 1
DPR access by the firmware
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
ACK
PID
Load In Progress
Write
Set by the firmware
Microcontroller Load Data in FIFO
USB Device
PID
Data IN
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Read
Read and Write at the Same Time
NAK
PID
Cleared by Firmware
PID
DPR access by the hardware
Data IN
USB Bus
Data is Sent on USB Bus
Data IN 2?
2 nd Data Payload
3 rd Data Payload
1 st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
Payload in FIFO
Data IN 2
Cleared by Hw
AT91CAP7E
?
ACK
PID
Cleared by
Firmware
Interrupt
Pending
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