AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 510

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

510
AT91CAP7E
21 Static Memory Controller (SMC) ......................................................... 131
21.1Description ..........................................................................................................131
21.2I/O Lines Description ...........................................................................................131
21.3Multiplexed Signals .............................................................................................131
21.4Application Example ............................................................................................132
21.6Product Dependencies ........................................................................................132
21.8External Memory Mapping ..................................................................................133
21.9Connection to External Devices ..........................................................................133
21.12Standard Read and Write Protocols ..................................................................137
21.20Automatic Wait States .......................................................................................146
21.25Data Float Wait States ......................................................................................150
21.29External Wait .....................................................................................................154
21.34Slow Clock Mode ...............................................................................................160
21.37Asynchronous Page Mode ................................................................................163
20.11.2Pull-up Control 122
20.12.3Static Memory Controller 122
20.13.4SDRAM Controller 122
20.14.5CompactFlash Support 122
20.15.6NAND Flash Support 127
21.5.1Hardware Interface 132
21.7.1I/O Lines 132
21.10.1Data Bus Width 133
21.11.2Byte Write or Byte Select Access 133
21.13.1Read Waveforms 138
21.14.2Read Mode 140
21.15.3Write Waveforms 142
21.16.4Write Mode 144
21.17.5Coding Timing Parameters 145
21.18.6Reset Values of Timing Parameters 146
21.19.7Usage Restriction 146
21.21.1Chip Select Wait States 146
21.22.2Early Read Wait State 147
21.23.3Reload User Configuration Wait State 149
21.24.4Read to Write Wait State 150
21.26.1READ_MODE 150
21.27.2TDF Optimization Enabled (TDF_MODE = 1) 152
21.28.3TDF Optimization Disabled (TDF_MODE = 0) 152
21.30.1Restriction 154
21.31.2Frozen Mode 155
21.32.3Ready Mode 157
21.33.4NWAIT Latency and Read/write Timings 159
21.35.1Slow Clock Mode Waveforms 160
21.36.2Switching from (to) Slow Clock Mode to (from) Normal Mode 161
21.38.1Protocol and Timings in Page Mode 163
8549A–CAP–10/08