AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 317

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

28.3
Figure 28-3. Application Block Diagram: Single Master/Multiple Slave Implementation
28.4
Table 28-1.
28.5
28.5.1
28.5.2
8549A–CAP–10/08
Pin Name
MISO
MOSI
SPCK
NPCS1-NPCS3
NPCS0/NSS
Application Block Diagram
Signal Description
Product Dependencies
I/O Lines
Power Management
Signal Description
SPI Master
The pins used for interfacing the compliant external devices are multiplexed with PIO lines. The
programmer must first program the PIOA controller to select the SPI I/O alternate functions.
The SPI may be clocked through the Power Management Controller (PMC), thus the program-
mer must first configure the PMC to enable the SPI clock.
Pin Description
Master In Slave Out
Master Out Slave In
Serial Clock
Peripheral Chip Selects
Peripheral Chip Select/Slave Select
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
NPCS3
NC
Output
Output
Master
Input
Output
Output
Type
SPCK
MISO
MOSI
NSS
SPCK
MISO
MOSI
NSS
SPCK
MISO
MOSI
NSS
Slave
Output
Input
Input
Unused
Input
Slave 0
Slave 1
Slave 2
AT91CAP7E
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