AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 178

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

SDRAMC_A[12:0]
Figure 22-2. Write Burst, 32-bit SDRAM Access
22.6.2
178
D[31:0]
SDWE
SDCS
SDCK
RAS
CAS
AT91CAP7E
SDRAM Controller Read Cycle
Row n
parameters, additional clock cycles are inserted between precharge/active (t
active/write (t
Configuration Register” on page
The SDRAM Controller allows burst access, incremental burst of unspecified length or single
access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus
maximizing performance of the SDRAM. If row and bank addresses do not match the previous
row/bank address, then the SDRAM controller automatically generates a precharge command,
activates the new row and starts the read command. To comply with the SDRAM timing param-
eters, additional clock cycles on SDCK are inserted between precharge and active commands
(t
uration register of the SDRAM Controller. After a read command, additional wait states are
generated to comply with the CAS latency (1, 2 or 3 clock delays specified in the configuration
register).
For a single access or an incremented burst of unspecified length, the SDRAM Controller antici-
pates the next access. While the last value of the column is returned by the SDRAM Controller
on the bus, the SDRAM Controller anticipates the read to the next column and thus anticipates
the CAS latency. This reduces the effect of the CAS latency on the internal bus.
For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads
to the best performance. If the burst is broken (border, busy mode, etc.), the next access is han-
dled as an incrementing burst of unspecified length.
RP
) and between active and read command (t
t
RCD
= 3
col a
RCD
Dna
) commands. For definition of these timing parameters, refer to the
col b
Dnb
col c
Dnc
187. This is described in
col d
Dnd
col e
Dne
RCD
col f
Dnf
). These two parameters are set in the config-
col g
Dng
Figure 22-2
col h
Dnh
col i
Dni
below.
col j
Dnj
RP
) commands and
col k
Dnk
8549A–CAP–10/08
“SDRAMC
col l
Dnl