AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 509

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8549A–CAP–10/08
19 Bus Matrix ............................................................................................. 103
20 External Bus Interface (EBI) ................................................................ 115
18.2Block Diagram .......................................................................................................97
18.3I/O Lines Description .............................................................................................97
18.4Product Dependencies ..........................................................................................97
18.6Functional Description ...........................................................................................97
18.7Shutdown Controller (SHDWC) User Interface .....................................................98
19.1Description ..........................................................................................................103
19.2Memory Mapping .................................................................................................103
19.3Special Bus Granting Mechanism .......................................................................103
19.7Arbitration ............................................................................................................104
19.8Arbitration Rules ..................................................................................................104
19.13AHB Generic Bus Matrix User Interface ............................................................106
20.1Overview .............................................................................................................115
20.2Block Diagram .....................................................................................................116
20.3I/O Lines Description ...........................................................................................117
20.4Application Example ............................................................................................118
20.7Product Dependencies ........................................................................................121
20.9Functional Description .........................................................................................122
18.5.1Power Management 97
18.8.1Register Mapping 98
18.9.2Shutdown Control Register 99
18.10.3Shutdown Mode Register 100
18.11.4Shutdown Status Register 101
19.4.1No Default Master 103
19.5.2Last Access Master 103
19.6.3Fixed Default Master 103
19.9.1Undefined Length Burst Arbitration 104
19.10.2Slot Cycle Limit Arbitration 105
19.11.3Round-Robin Arbitration 105
19.12.4Fixed Priority Arbitration 105
19.14.1Bus Matrix Master Configuration Registers 108
19.15.2Bus Matrix Slave Configuration Registers 109
19.16.3Bus Matrix Priority Registers A For Slaves 110
19.17.4Bus Matrix Priority Registers B For Slaves 110
19.18.5Bus Matrix Master Remap Control Register 111
19.19.6EBI Chip Select Assignment Register 112
19.20.7Matrix USB Pad Pull-up Control Register 113
20.5.1Hardware Interface 118
20.6.2Connection Examples 121
20.8.1I/O Lines 121
20.10.1Bus Multiplexing 122
AT91CAP7E
509