AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 51

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.5.3
Figure 11-7. Write to FPGA
Figure 11-8. Read from FPGA
8549A–CAP–10/08
PIO-FPGA Waveforms
WR / RD_
AHB CLK
START
DATA
WR / RD_
AHB CLK
START
DATA
t1
t1
data
NOTE
Figure
The access time is calculated as the sum of:
Using the GCC compiler with maximum optimizations, the system takes approximately 55
AHB cycles to perform the write operation to the FPGA.
Figure 11-8
Address Phase
Address Phase
Address
11-7shows the PIO timing when writing to FPGA.
Address
These algorithms are for a basic transfer, a more sophisticated algorithm is
necessary to establish a proper communication between the ARM microcontroller
and the FPGA.
shows the PIO timing when reading from the FPGA.
PIO_DATA_DIR = INPUT; // Set PIO-Data direction as input to receive the
DELAY(WAIT_FOR_FPGA); // wait for the FPGA to send the data
DATA_FROM_FPGA = *PIO_DATA; // this is the end of read cycle
T
access-Pio
t2
t2
= t1 + address phase + t2 + data phase
Data from FPGA
Data Phase
Data Phase
Data
AT91CAP7E
51