AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet
AT91CAP7E-NA-ZJ
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AT91CAP7E-NA-ZJ Summary of contents
Page 1
... Two External Interrupt Sources and one Fast Interrupt Source, Spurious interrupt protected • Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention ® ® Thumb Processor ® and CompactFlash Customizable ® Microcontroller AT91CAP7E Preliminary 8549A–CAP–10/08 ...
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... Package Options: 144 LQFP, 176 LQFP, 208 PQFP, 144 LFBGA, 176TFBGA, 208 TFBGA, 225 LFBGA 1. Description The AT91CAP7E semi-custom System on a Chip (SoC microcontroller with a special interface that allows logic in an external FPGA to be mapped directly onto its internal Amba High-speed Bus (AHB). This FPGA interface includes multiple master and slave channels ...
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... Block Diagram Figure 2-1. AT91CAP7E Block Diagram JTAGSEL TDI TDO JTAG TMS Boundary Scan TCK NTRST System Controller TST AIC FIQ IRQ0-IRQ1 DRXD DBGU DTXD PDC PCK0-PCK3 PLLA PLLRCA PMC PLLB XIN OSC XOUT WDT PIT RC OSC GPBREG XIN32 OSC RTT ...
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... Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output PLLRCA PLL A Filter PCK0 - PCK3 Programmable Clock Output AD0 ADC Input 0 AD1 ADC Input 1 AD2 ADC Input 2 AD3 ADC Input 3 AT91CAP7E 4 Type Power Supplies Power Power Power Power Power Power Power Power Ground Ground Ground ...
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... I/O Input Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input Input PIO Controller - PIOA and PIOB I/O AT91CAP7E Active Level Comments Analog access via MPIO86 pin Analog access via MPIO87 pin Analog access via MPIO88 pin Analog access via MPIO89 pin ...
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... Bank Select SDWE SDRAM Write Enable RAS - CAS Row and Column Signal SDA10 SDRAM Address 10 Line Universal Synchronous Asynchronous Receiver Transmitter USART SCKx USARTx Serial Clock AT91CAP7E 6 Type I/O External Bus Interface - EBI I/O Output Input Static Memory Controller - SMC Output ...
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... FPGA Interface- FPIF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AT91CAP7E Active Level Comments access via PIOA access via PIOA access via PIOA access via PIOA access via PIOA access via PIOA access via PIOA access via PIOA ...
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... Master A serial address lines MA_START Master A serial start MB_C Master B serial control MB_D0 - MB_D1 Master B serial data lines MB_A0 - MB_A1 Master B serial address lines AT91CAP7E 8 Active Type Level Comments access via PIOB/ mapped to I/O MPIO14 thru MPIO15 access via PIOB/ mapped to ...
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... Slave ZBT RAM serial control SZBT_D0 - SZBT_D3 Slave ZBT RAM serial data lines SZBT_A0 - SZBT_A3 Slave ZBT RAM serial address lines SZBT_START Slave ZBT RAM serial start 8549A–CAP–10/08 AT91CAP7E Active Type Level Comments Pull-up resistor; mapped to I/O Low MPIO Pull-up resistor ...
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... Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function FPIF_SCLK FPIF Serial Clock FPIF_SCLK_FEEDBK FPIF Serial Clock Feedback FPIF_RESETN FPIF Reset AT91CAP7E 10 Active Type Level Comments Input mapped to MPIO Output mapped to MPIO Pull-up resistor; mapped to Input Low MPIO 8549A–CAP–10/08 ...
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... Package and Pinout The AT91CAP7E is available in a RoHS-compliant 225-ball LFBGA 13x13x1.4mm, 0.8 mm ball pitch. 4.1 Mechanical Overview of the 225-ball LFBGA Package Figure 4-1 description is given in the Mechanical Characteristics section of the product datasheet. Figure 4-1. 4.2 225-ball LFBGA Package Pinout Warning: This package pinout is preliminary and is subject to change. ...
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... Table 4-1. AT91CAP7E Pinout for 225-ball LFBGA Package (Continued) Pin Signal Name Pin B4 MPIO46 F1 B5 PA5 F2 B6 MPIO24 F3 B7 MPIO15 F4 B8 MPIO11 F5 B9 MPIO22 F6 B10 MPIO44 F7 B11 MPIO06 F8 B12 MPIO04 F9 B13 MPIO37 F10 B14 MPIO74 F11 B15 A20 F12 C1 MPIO52 F13 ...
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... Table 4-1. AT91CAP7E Pinout for 225-ball LFBGA Package (Continued) Pin Signal Name Pin D10 MPIO42 H7 D11 MPIO77 H8 D12 MPIO02 H9 8549A–CAP–10/08 Signal Name Pin Signal Name GND M4 XIN32 GND M5 GNDOSC32 GND M6 MPIO83/AD1 AT91CAP7E Pin Signal Name 13 ...
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... Power Consumption Note: The AT91CAP7E consumes about 600 μA of static current on VDDCORE at typical conditions (1.2V, 25°C). On VDDBU, the current does not exceed 30 μA at typical conditions. For dynamic power consumption, the AT91CAP7E consumes about 0.33 mW/MHz of power or 275 μA/MHz of current on VDDCORE at typical conditions (1.2V, 25°C) and with the ARM sub- system running full-performance algorithm with on-chip memories, and no peripherals active ...
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... This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables. 6.5 Shut Down Logic pins The SHDN pin is an output only, which is driven by the Shut Down Controller only at low level. It can be tied high with an external pull-up resistor at VDDBU only. 8549A–CAP–10/08 AT91CAP7E 15 ...
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... Selection is made by BMS pin sampled at reset • Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory – Allows Handling of Dynamic Exception Vectors AT91CAP7E 16 or fixed default master internal boot, one for external boot, one after remap ...
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... Master 1 Master 2 Master 3 7.3.2 Matrix Slaves The Bus Matrix of the AT91CAP7E manages nine Slaves. Each Slave has its own arbiter, thus allowing to program a different arbitration per Slave. There are four independent slaves available for the FPGA Interface. Table 7-2. Slave 0 Slave 1 ...
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... The bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Figure 8-1. AT91CAP7E Product Memory Mapping 256M Bytes 8 x 256M Bytes 2,048M bytes 6 x 256M Bytes ...
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... Boot Memory The AT91CAP7E Matrix manages a boot memory which depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved at this effect. If BMS is detected at logic 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface ...
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... Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multi-bank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities AT91CAP7E support 8549A–CAP–10/08 ...
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... Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency and 3 supported • Auto Precharge Command not used 8549A–CAP–10/08 AT91CAP7E 21 ...
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... The System Controller User Interface also includes control registers for configuring the AHB Matrix and the chip configuration. The chip configuration registers allow setting the EBI chip select assignment for external memories. AT91CAP7E 22 8549A–CAP–10/08 ...
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... System Controller Block Diagram Figure 9-1. AT91CAP7E System Controller Block Diagram wdt_irq dbgu_irq pmc_irq NRST VDDCORE VDDCOR E VDDBU VDDBU SHDN WKUP XIN32 SLOW CLOCK XOUT32 XIN MAIN XOUT PLLRCA PLLA PLLB P A0-P A31 PB0-PB31 8549A–CAP–10/08 System Controller irq0-irq1 ...
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... FD00 0xFFFF FD10 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 0xFFFF FD50 0xFFFF FD60 0xFFFF FDB0 0xFFFF FFFF AT91CAP7E 24 Figure 9-2 shows where the User Interfaces for the System Controller peripherals fit Peripheral Name Reserved SDRAMC SDRAM Controller SMC Static Memory Controller ...
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... Embeds the Low Power, fast start-up 32kHz RC Oscillator – Provides the default Slow Clock SLCK to the system – The SLCK is required for AT91CAP7E to start-up because it is the default clock for • Embeds the Low Power 32768Hz Slow Clock Oscillator – Requires an external 32768Hz crystal – ...
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... Idle Mode, processor stopped waiting for an interrupt – Slow Clock Mode, processor and peripherals running at low frequency – Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, – Backup Mode, Main Power Supplies off, VDDBU powered by a battery AT91CAP7E 26 Clock Generator XIN32 ...
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... Figure 9-4. AT91CAP7E Power Management Controller Block Diagram SLCK MAINCK PLLACK PLLBCK 9.7 Periodic Interval Timer • Includes a 20-bit Periodic Counter, with less than 1μs accuracy • Includes a 12-bit Interval Overlay Counter • Real Time OS or Linux/WinCE compliant tick generator 9.8 Watchdog Timer • ...
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... Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter AT91CAP7E 28 enabled processor Generator ...
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... PIOA has multiplexing of two peripheral functions per I/O Line (see section Controller A Multiplexing” on page • PIOB multiplexing is controlled by the FPGA Interface (see section Multiplexing” on page 8549A–CAP–10/08 the ARM Processor’s ICE Interface 36) 47) AT91CAP7E 10.4.1 ”PIO 11.4.2 ”PIO Controller B 29 ...
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... Enables the external crystal oscillator • OSC32K_SEL: Slow clock source select 0: Selects internal RC as source of slow clock 1: Selects external crystal and source of slow NOTE: After setting OSC32K_XT_EN bit, wait till 1. chip slow clock timing before setting OSC32K_SEL bit. AT91CAP7E 30 Name SYSC_OSCMR SYSC_GPBR1 ...
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... General Purpose Backup Register Register Name: Access Type: Reset Value: 0x0 • GPBRx: General Purpose Backup Register These are user programmable registers that are powered by the backup power supply (VDDBU). 8549A–CAP–10/08 SYSC_GPBRx Read/Write GPBRx GPBRx GPBRx GPBRx AT91CAP7E ...
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... Both the standard peripherals and any APB peripherals implemented in the MPBlock are mapped in the upper 256M bytes of the address space between the addresses 0xFFFA 0000 and 0xFFFE FFFF. Each User Peripheral is allocated 16K bytes of address space as shown below in Figure 10-1. AT91CAP7E 32 8549A–CAP–10/08 ...
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... Figure 10-1. AT91CAP7E Peripheral Mapping 0xFFFA 0000 TC0, TC1, TC2 0xFFFA 3FFF 0xFFFA 4000 0xFFFA 7FFF 0xFFFA 8000 0xFFFA BFFF 0xFFFA C000 0xFFFA FFFF 0xFFFB 0000 USART0 0xFFFB 3FFF 0xFFFB 4000 USART1 0xFFFB 7FFF 0xFFFB 8000 0xFFFB BFFF 0xFFFB C000 0xFFFB FFFF ...
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... The AT91CAP7E embeds some of the most common peripherals. Additional peripherals can be readily implemented in the external FPGA by the customer, and mapped direcly on the APB. The table below defines the Peripheral Identifiers of the AT91CAP7E. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller ...
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... Peripherals Signals Multiplexing on I/O Lines The AT91CAP7E features two PIO controllers, PIOA which multiplexes the I/O lines of the stan- dard peripheral set and PIOB which multiplexes the FPGA Interface through MPIO. Each PIO Controller controls lines. On PIOA, each line can be assigned to one of two peripheral functions ...
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... PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 AT91CAP7E 36 Multiplexing on PIO Controller A Peripheral A Peripheral B FIQ DBG_DRXD NWAIT DBG_DTXD NCS4/CFCS0 USART0_SCK0 CFCE1 USART0_RTS0 A25/CFRNW USART0_CTS0 NANDOE USART0_TXD0 NANDWE USART0_RXD0 NCS6 ...
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... Using FIQ prevents using the Debug Unit. Using IRQ0 prevents the use of SPI_NPCS0. Using IRQ1 prevents the use of SPI_NPCS1. 8549A–CAP–10/08 Multiplexing on PIO Controller A Peripheral A Peripheral B D29 TIMER1_TIOB1 D30 TIMER2_TIOA2 D31 TIMER2_TIOB2 11.4.2 ”PIO Controller B Multiplexing” on page AT91CAP7E Reset State 47). 37 ...
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... ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo AT91CAP7E 38 peripherals Sensors and data per chip select 8549A–CAP–10/08 ...
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... Individual enable and disable of each channel • Multiple trigger sources: – Hardware or software trigger – External trigger pin • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all 8549A–CAP–10/08 enabled channels AT91CAP7E 39 ...
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... AT91CAP7E 40 8549A–CAP–10/08 ...
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... Description The FPGA Interface (FPIF) module provides a means to connect an external FPGA directly to the AT91CAP7E internal AHB Bus. This interface is implemented in the metal-programmable logic block (MP Block) that is provided as part of the AT91CAP7S customizable microcontroller platform. Therefore the interface is constrained to access the AHB Bus through the Masters and Slaves already pre-defined for the MP block. • ...
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... AHB clock cycles. The specific number of clock cycles depends on the ratio between the CAP7E MCK and FPIF_SCLK and the ratio between the FPGA AHB clock and the FPIF_SCLK. The lower those two ratios are, the fewer AHB clocks it will take for a single transfer. AT91CAP7E 42 ZBT ARM7TDMI ...
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... AHB protocol. The number of wait cycles inserted by the FSM depends upon the two ratios between the CAP7E and FPGA AHB clocks and the FPGA Interface Serial Clock (FPIF_SCLK). Therefore, the smaller those ratios, the less number of wait states are inserted. AT91CAP7E ZBT Interface S0 FPGA ...
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... In this case, the data transfer rate between the CAP7E and the FPGA is reduced, but the data bandwidth increases because now 2 AHB interfaces are enabled. Figure 11-4 interface. AT91CAP7E 44 Shifter: This block is controlled by the FSM, and it handles all the data shifting (serializing) between the CAP7E-FPGA and transfers 2 bits per cycle. If the FPIF_SCLK rate is set @100mhz, then the shifters transfer 200Mbps ...
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... Serial Data to CAP7E t6 shows all the timing for a transfer between the CAP7E and the FPGA. t1: Time for a standard 2 cycles AHB t2: Time to transfer the request to FPGA (4 cycles single AHB interface, 8 cycles dual AHB interface). AT91CAP7E FPGA FPGA AHB CLK AHB S0 FPGA FSM ...
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... Table 11-1. Mode-bits description AT91CAP7E 46 t3: Time for FPGA-Peripheral response t4: Time to transfer response back to CAP7E (4 cycles single AHB interface, 8 cycles dual AHB interface) t5: Time to read back the response/data from FPGA to the internal CAP7E AHB bus t6: Time for introduced wait cycles access ...
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... PB11 FPP6_RX_RDY PB12 FPP6_TX_SIZE0 PB13 FPP6_TX_SIZE1 PB14 FPP6_RX_SIZE0 PB15 FPP6_RX_SIZE1 FPP7_TX_BFFR_ PB16 EMPTY FPP7_RX_BFFR_ PB17 FULL FPP7_CHNL_TX_ PB18 END FPP7_CHNL_RX PB19 _END PB20 FPP7_TX_RDY PB21 FPP7_RX_RDY PB22 FPP7_TX_SIZE0 PB23 FPP7_TX_SIZE1 PB24 FPP7_RX_SIZE0 PB25 FPP7_RX_SIZE1 PB26 APB_C PB27 APB_D0 AT91CAP7E Reset State 47 ...
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... MPIO41 MPIO42 MPIO43 MPIO44 MPIO45 MPIO46 MPIO47 MPIO48 MPIO49 MPIO50 MPIO51 MPIO52 MPIO53 MPIO54 MPIO55 MPIO56 MPIO57 AT91CAP7E 48 Multiplexing on PIO Controller B PIO Mode APB Mode PB28 APB_D1 PB29 APB_A0 PB30 APB_A1 PB31 APB_START MPIO Signal Assignments/Multiplexing Single Mode Dual Mode MA_C2 ...
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... MPIO Signal Assignments/Multiplexing Single Mode Dual Mode SC_D0 SD_D1 SC_D1 SD_A0 SC_D2 SD_A1 SC_D3 SC_C SC_A0 SC_D0 SC_A1 SC_D1 SC_A2 SC_A0 SC_A3 SC_A1 SC_START SC_START SD_START SD_START SZBT_C2 SZBT_C1 SZBT_D0 SZBT_D1 SZBT_D2 SZBT_D3 SZBT_A0 SZBT_A1 SZBT_A2 SZBT_A3 SZBT_START FPIF_SCLK FPIF_SCLK_FEEDB K FPIF_RESETN AT91CAP7E 49 ...
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... Based on the resources shown above, we can define a software algorithm to transfer data from/to FPGA. Þ write_to_fpga: Algorithm to write 32 bits of data to FPGA, this assumes that, the Þ read_from_fpga: Algorithm to read data from the FPGA, this assumes that, the direction AT91CAP7E 50 Figure 11-6 shows the 32+2 PIO interface to a FPGA. ...
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... ARM microcontroller and the FPGA. 11-7shows the PIO timing when writing to FPGA. Address t2 Address Phase Data Phase address phase + t2 + data phase access-Pio shows the PIO timing when reading from the FPGA. Address Data from FPGA t2 Address Phase Data Phase AT91CAP7E Data 51 ...
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... Figure 11-9. EBI driving the FPGA ARM Microcontroller ARM EBI SRAM Controller System 11.6.2 EBI TIming Figure 11-10 and NOTE AT91CAP7E 52 shows the ARM Microcontroller driving the FPGA through the EBI. The selected Address Data NBS FPGA Logic NCS NRD NWE ...
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... WCK A [25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NRD NCS D [S1:D] NCS_RD_SETUP Figure 11-11. Write Cycle MCK A [25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NWE_SETUP NCS_WR_SETUP 8549A–CAP–10/08 NRD_SETUP NRD_PULSE NCS_RD_PULSE NRD_CYCLE NWE_PULSE NCS_WR_PULSE NWE_CYCLE AT91CAP7E NRD_HOLD NCS_RD_HOLD NWE_HOLD NCS_WR_HOLD 53 ...
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... AT91CAP7E 54 8549A–CAP–10/08 ...
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... Mode changes may be made under software control, or may be brought about by external inter- rupts or exception processing. Most application programs execute in User mode. The non-user 8549A–CAP–10/08 ® High-performance 32-bit Instruction Set ® High Code Density 16-bit Instruction Set AT91CAP7E ® ® and 16-bit Thumb instruction sets, allow- 55 ...
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... R14 holds the return address after a subroutine call. R13 is used (by software convention stack pointer. Table 12-1. User and System Mode R10 R11 R12 R13 R14 PC CPSR AT91CAP7E 56 ARM7TDMI ARM Modes and Registers Layout Supervisor Mode Abort Mode ...
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... More than one exception can occur in the same time. When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state. 8549A–CAP–10/08 supports five types of exception and a privileged processing mode for each type. AT91CAP7E 57 ...
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... AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT AT91CAP7E 58 gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply ...
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... Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte AT91CAP7E Mnemonic Operation SWPB Swap Byte MRC Move From Coprocessor STC Store From Coprocessor Mnemonic Operation MVN ...
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... Table 12-3. Mnemonic LDRSH LDMIA PUSH AT91CAP7E 60 Thumb Instruction Mnemonic List Operation Load Signed Halfword Load Multiple Push Register to stack Mnemonic Operation LDRSB Load Signed Byte STMIA Store Multiple POP Pop Register from stack 8549A–CAP–10/08 ...
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... CAP7E Debug and Test 13.1 Overview The AT91CAP7E features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as down- loading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communica- tion Channel ...
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... A software debugger running on a personal computer provides the user interface for ICE/JTAG interface. Figure 13-2. Application Debug and Trace Environment Example AT91CAP7E 62 shows a complete debug environment example. The ICE/JTAG inter- ICE/JTAG ...
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... Test Mode Select ICE and JTAG Test Clock Test Data In Test Data Out Test Mode Select Test Reset Signal JTAG Selection Debug Unit Debug Receive Data Debug Transmit Data AT91CAP7E Tester Type Active Level Input/Output Low Input High Input Input Output ...
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... A specific register, the Debug Unit Chip ID Register (DBGU_CIDR), gives information about the product’s internal configuration and its version. The AT91CAP7E Debug Unit Chip ID value is 0x8377 09xx on 32-bit width (1000 0011 0111 0111 0000 1001 010x xxxx). The last five bits of the register are reserved for a version number. ...
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... The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Each customer’s AT91CAP7E product may have its own unique BSR. For a full description of this BSR, see the appropriate product-specifc BSDL file. ...
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... AT91CAP7E 66 8549A–CAP–10/08 ...
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... NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. 8549A–CAP–10/08 Reset Controller Startup Counter Reset State Manager user_reset NRST Manager nrst_out exter_nreset SLCK AT91CAP7E rstc_irq proc_nreset periph_nreset backup_neset 67 ...
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... This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. AT91CAP7E 68 Figure 14-2 shows the block diagram of the NRST Manager. ...
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... SLCK MCK Backup Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) 8549A–CAP–10/08 shows how the General Reset affects the reset signals. Startup Time Processor Startup = 3 cycles XXX EXTERNAL RESET LENGTH = 2 cycles AT91CAP7E Any Freq. 0x0 = General Reset XXX 69 ...
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... The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three- cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. AT91CAP7E 70 Resynch. Processor Startup ...
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... The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn- chronously to SLCK. 8549A–CAP–10/ Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH AT91CAP7E Processor Startup = 3 cycles 0x4 = User Reset ...
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... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. AT91CAP7E 72 Any Freq. Resynch. ...
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... A User Reset cannot be entered. 14.3.5 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: 8549A–CAP–10/08 SLCK Any MCK Freq. Processor Startup = 3 cycles Any XXX NRST proc_nreset signal. AT91CAP7E 0x2 = Watchdog Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 73 ...
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... Reset Controller (RSTC) Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. AT91CAP7E 74 2 cycle resynchronization Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR ...
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... EXTRST – – – – – – – – – – – – AT91CAP7E – – – PERRST – PROCRST 26 25 – – – SRCMP NRSTL 10 9 RSTTYP 2 1 – URSTS 24 16 – 8 – – ...
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... The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length AT91CAP7E 76 Comments Both VDDCORE and VDDBU rising VDDCORE rising ...
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... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 μs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 8549A–CAP–10/08 AT91CAP7E (ERSTL+1) Slow Clock cycles. This 77 ...
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... AT91CAP7E 78 8549A–CAP–10/08 ...
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... Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 8549A–CAP–10/08 set 0 RTT_SR RTTINC reset 1 0 32-bit Counter read RTT_SR reset CRTV RTT_SR ALMS set = ALMV AT91CAP7E RTT_MR RTTINCIEN rtt_int RTT_MR ALMIEN rtt_alarm 32 seconds, corre- 79 ...
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... RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91CAP7E 80 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
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... Register Mapping Table 15-1. Real-time Timer Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 8549A–CAP–10/08 Name Access RTT_MR Read/Write RTT_AR Read/Write RTT_VR Read-only RTT_SR Read-only AT91CAP7E Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 81 ...
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... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91CAP7E 82 RTT_MR Read/Write 29 ...
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... Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.4.4 Real-time Timer Value Register Register Name: Access Type • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 8549A–CAP–10/08 RTT_AR Read/Write ALMV ALMV ALMV ALMV RTT_VR Read-only CRTV CRTV CRTV CRTV AT91CAP7E ...
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... The Real-time Alarm occured since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91CAP7E 84 RTT_SR Read-only ...
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... PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. 8549A–CAP–10/08 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR AT91CAP7E set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR PICNT ...
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... PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface AT91CAP7E 86 APB cycle MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR Figure 16-2 APB cycle ...
Page 87
... The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. 8549A–CAP–10/08 Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR – – – – – PIV PIV AT91CAP7E Access Reset Value Read/Write 0x000F_FFFF Read-only 0x0000_0000 Read-only 0x0000_0000 Read-only 0x0000_0000 – PITIEN PITEN PIV ...
Page 88
... Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. AT91CAP7E – – – ...
Page 89
... Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 8549A–CAP–10/ PICNT CPIV CPIV AT91CAP7E CPIV ...
Page 90
... AT91CAP7E 90 8549A–CAP–10/08 ...
Page 91
... Watchdog period seconds (with a typical Slow Clock of 32.768 kHz). 8549A–CAP–10/08 WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset AT91CAP7E reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 91 ...
Page 92
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91CAP7E 92 8549A–CAP–10/08 ...
Page 93
... Watchdog Error WDT_CR = WDRSTT Name WDT_CR WDT_MR WDT_SR WDT_CR Write-only KEY – – – – – – – – – AT91CAP7E Watchdog Underflow if WDRSTEN WDRSTEN is 0 Access Reset Value Write-only - Read/Write Once 0x3FFF_2FFF Read-only 0x0000_0000 – – – – – – – ...
Page 94
... The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable AT91CAP7E 94 WDT_MR Read/Write Once 29 28 ...
Page 95
... At least one Watchdog error occurred since the last read of WDT_SR. 8549A–CAP–10/08 WDT_SR Read-only – – – – – – – – – – – – AT91CAP7E – – – – – – – – – – WDERR WDUNF 95 ...
Page 96
... AT91CAP7E 96 8549A–CAP–10/08 ...
Page 97
... The Shutdown Controller manages the main power supply so supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. 8549A–CAP–10/08 read SHDW_SR reset WAKEUP0 SHDW_SR set read SYSC_SHSR reset RTTWK SHDW_MR SHDW_SR set AT91CAP7E SLCK Wake-up SHDN Shutdown Output Controller SHDW_CR Shutdown SHDW Type Input Output 97 ...
Page 98
... Register Mapping Table 18-2. Shutdown Controller (SHDWC) Registers Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register AT91CAP7E 98 SHDN to the shutdown input of the DC/DC Converter pro- SHDN by writing the Shutdown Control Register Name Access SHDW_CR Write-only SHDW_MR ...
Page 99
... KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 8549A–CAP–10/08 SHDW_CR Write-only KEY – – – – – – – – – pin. AT91CAP7E – – – – – – – – SHDW 99 ...
Page 100
... Because of the internal synchronization of WKUP0, the (CPTWK Slow Clock cycles after the event on WKUP. • RTTWKEN: Real-time Timer Wake-up Enable 0 = The RTT Alarm signal has no effect on the Shutdown Controller The RTT Alarm signal forces the de-assertion of the AT91CAP7E 100 – ...
Page 101
... At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. 8549A–CAP–10/08 SHDW_SR Read-only – – – – – – – – – – – – AT91CAP7E – – – – – RTTWK – – – – – WAKEUP0 101 ...
Page 102
... AT91CAP7E 102 8549A–CAP–10/08 ...
Page 103
... FIXED_DEFMSTR field selects a fixed default master pro- vided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface description. 8549A–CAP–10/08 ® Advance Peripheral Bus and provides 6 Special Function Registers AT91CAP7E 103 ...
Page 104
... Sixteen beat bursts: Predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG). AT91CAP7E 104 104. See “Undefined Length Burst Arbitration” on Section 19.5 ”Arbitration See “ ...
Page 105
... For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and MATRIX_PRBS). 8549A–CAP–10/08 AT91CAP7E 105 ...
Page 106
... Priority Register A for Slave 6 0x00B4 Priority Register B for Slave 6 0x00B8 Unused - Priority Register A for Slave 7 0x00BC Unused - Priority Register B for Slave 7 0x00C0 Priority Register A for Slave 8 0x00C4 Priority Register B for Slave 8 AT91CAP7E 106 Register Mapping Name MATRIX_MCFG0 MATRIX_MCFG1 MATRIX_MCFG2 MATRIX_MCFG3 - - MATRIX_SCFG0 ...
Page 107
... EBI Chip Select Assignment Register 0x0134 USB Pull-up Control Register 0x0138 - 0x01F8 Reserved 8549A–CAP–10/08 Name Access MATRIX_PRAS9 Read/Write MATRIX_PRBS9 Read/Write - - MATRIX_MRCR Read/Write – – MATRIX_EBICSA Read/Write MATRIX_USBPCR Read/Write – – AT91CAP7E Reset Value 0x00000000 0x00000000 - 0x00000000 – 0x00000000 0x00000000 – 107 ...
Page 108
... The undefined length burst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end. 3: Eight Beat Burst The undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end. 4: Sixteen Beat Burst The undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end. AT91CAP7E 108 MATRIX_MCFG0...MATRIX_MCFG3 Read/Write 29 ...
Page 109
... DEFMSTR_TYPE to 0. • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration 2: Reserved 3: Reserved 8549A–CAP–10/08 MATRIX_SCFG0...MATRIX_SCFG9 (MATRIX_SCFG7 unused) Read/Write – – – FIXED_DEFMSTR – – – SLOT_CYCLE AT91CAP7E – ARBT DEFMSTR_TYPE – – – 109 ...
Page 110
... MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. AT91CAP7E 110 MATRIX_PRAS0...MATRIX_PRAS8 (MATRIX_PRAS7 unused) Read/Write M7PR – M5PR – M3PR – ...
Page 111
... Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master 8549A–CAP–10/08 MATRIX_MRCR Read/Write 0x0000_0000 – – – – – – – – – RCB5 RCB4 RCB3 AT91CAP7E – – – – – – – – – RCB2 RCB1 RCB0 111 ...
Page 112
... EBI Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. • EBI_DBPUC: EBI Data Bus Pull-Up Configuration 0 = EBI D0 - D15 Data Bus bits are internally pulled-up to the VDDIO power supply EBI D0 - D15 Data Bus bits are not internally pulled-up. AT91CAP7E 112 MATRIX_EBICSA Read/Write ...
Page 113
... Register Name: Access Type: Reset PUP_IDLE UDP_PUP_ON • PUP_IDLE: Pull-up Idle 0: Pad pull-up set on higher resistance 1: Pad pull-up set on lower resistance • UDP_PUP_ON: UDP Pad Pull-up Enable 0: Pad pull-up disabled 1: Pad pull-up enabled 8549A–CAP–10/08 MATRIX_USBPCR Read/Write 0x0000_0000 AT91CAP7E 113 ...
Page 114
... AT91CAP7E 114 8549A–CAP–10/08 ...
Page 115
... Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus bits eight chip select lines (NCS[7:0]) and several control pins that are generally multiplexed between the different external Memory Controllers. 8549A–CAP–10/08 AT91CAP7E ® -based device. The 115 ...
Page 116
... Block Diagram Figure 20-1 Figure 20-1. Organization of the External Bus Interface Bus Matrix AHB Address Decoders AT91CAP7E 116 shows the organization of the External Bus Interface. External Bus Interface SDRAM Controller MUX Logic Static Memory Controller NAND Flash Logic CompactFlash Logic ...
Page 117
... NWR0 - NWR3 Write Signals NBS0 - NBS3 Byte Mask Signals SDA10 SDRAM Address 10 Line 8549A–CAP–10/08 EBI SMC EBI for CompactFlash Support EBI for NAND Flash Support SDRAM Controller AT91CAP7E Type Active Level I/O Output Input Low Output Low Output Low Output ...
Page 118
... A2 - A25 A[2:25] NCS0 CS NCS1/SDCS CS NCS2 CS NCS3/NANDCS CS NCS4/CFCS0 CS AT91CAP7E 118 details the connections between the two Memory Controllers and the EBI Pins and Memory Controllers I/O Lines Connections EBI Pins SDRAMC I/O Lines NBS1 Not Supported Not Supported SDRAMC_A[9:0] SDRAMC_A10 Not Supported ...
Page 119
... D16 - D31 – DQM0 A0 DQM2 A1 A[0:8] A[2:10] A9 – A10 – – – A[11:12] – – – BA0 – BA1 – – – – – – REG AT91CAP7E 4 x 8-bit 2 x 16-bit Static Static Devices Devices SMC ( (2) (3) WE NUB (2) (4) WE NUB Compact ...
Page 120
... NCS5/CFCS1 NCS6/NANDOE NCS7/NANDWE NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW CFCE1 CFCE2 SDCK SDCKE RAS CAS SDWE NWAIT (2) Pxx (2) Pxx (2) Pxx Note: AT91CAP7E 120 Pins of the Interfaced Device Compact SDRAM Flash SDRAMC – – (1) – CFRNW – – CS – – – – – (1) – ...
Page 121
... RAS BA0 A17/BA1 CAS BA1 DQM NBS2 128K x 8 SRAM A1-A17 D0-D7 A0-A16 D0-D7 D8-D15 CS OE NRD/NOE NRD/NOE WE A0/NWR0/NBS0 NWR1/NBS1 AT91CAP7E SDRAM D8-D15 D0-D7 CS CLK A0-A9, A11 A2-A11, A13 CKE SDWE A10 SDA10 WE BA0 A16/BA0 RAS BA1 A17/BA1 CAS DQM NBS1 ...
Page 122
... NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup- ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. AT91CAP7E 122 8549A–CAP–10/08 ...
Page 123
... Offset 0x0040 0000 Offset 0x0000 0000 The A22 pin of the EBI is used to drive the REG signal of the CompactFlash Device (except in True IDE mode). CompactFlash Mode Selection AT91CAP7E True IDE Alternate Mode Space True IDE Mode Space I/O Mode Space Common Memory Mode Space ...
Page 124
... CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. 20-4 on page 125 Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values. AT91CAP7E 124 CFCE1 DBW ...
Page 125
... A23 A22 NRD NWR0_NWE CFOE CFWE NRD NWR0_NWE and Table 20-9 on page 126 Table 20-9 on page 126 remain shared between all memory areas when the cor- CompactFlash Signals CS5A = 1 CFCS1 AT91CAP7E CompactFlash Logic CFOE 1 1 CFWE 1 0 CFIOR 1 CFIOW 1 1 CFIOR ...
Page 126
... The CompactFlash _WAIT sig- nal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the Static Memory Controller section. AT91CAP7E 126 Access to CompactFlash Device CompactFlash Signals ...
Page 127
... NCS6 and NCS7 (i.e., between 0x70000000 and 0x8FFF FFFF) may lead to an unpredictable outcome. 8549A–CAP–10/08 EBI D[15:0] A25/CFRNW NCS4/CFCS0 CD (PIO) A[10:0] A22/REG NRD/CFOE NWE/CFWE NWR1/CFIOR NWR3/CFIOW CFCE1 CFCE2 NWAIT AT91CAP7E CompactFlash Connector D[15:0] DIR /OE _CD1 _CD2 /OE A[10:0] _REG _OE _WE _IORD _IOWR _CE1 _CE2 _WAIT ...
Page 128
... NCS3 address space. The chip enable (CE) signal of the device and the ready/busy (R/B) sig- nals are connected to PIO lines. The CE signal then remains asserted even when NCS3 is not selected, preventing the device from returning to standby mode. AT91CAP7E 128 MUX Logic CS3A ...
Page 129
... Figure 20-7. NAND Flash Application Example Note: 8549A–CAP–10/08 D[7:0] A[22:21] NCS3/NANDCS EBI NCS6/NANDOE NCS7/NANDWE PIO PIO The External Bus Interface is also able to support 16-bits devices. AT91CAP7E AD[7:0] ALE CLE Not Connected NAND Flash NOE NWE CE R/B 129 ...
Page 130
... AT91CAP7E 130 8549A–CAP–10/08 ...
Page 131
... Byte-write or byte-select access see “Data Bus Width” on page 133 8-/16-bit or 32-bit data bus, see Byte-write or byte-select access, see 133 “Byte Write or Byte Select Access” on page 133 Byte-write or byte-select access see AT91CAP7E 8 Chip Selects and a 26-bit address bus. The Type Output Output Output ...
Page 132
... The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other putposes by the PIO Controller. AT91CAP7E 132 128K x 8 SRAM ...
Page 133
... This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 8549A–CAP–10/08 NCS2 NCS1 NCS0 shows how to connect a 512K x 8-bit memory on NCS2. Figure 21-5 AT91CAP7E Figure 21-2). NCS7 Memory Enable NCS6 Memory Enable NCS5 Memory Enable ...
Page 134
... Figure 21-3. Memory Connection for an 8-bit Data Bus Figure 21-4. Memory Connection for a 16-bit Data Bus Figure 21-5. Memory Connection for a 32-bit Data Bus SMC AT91CAP7E 134 D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[15:0] A[19:2] A1 NBS0 SMC NBS1 NWE NRD NCS[2] ...
Page 135
... Byte Select Access is used to connect two 16-bit devices. Figure 21-7 mode, on NCS3 (BAT = Byte Select Access). 8549A–CAP–10/08 Figure 21-6. shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access AT91CAP7E 135 ...
Page 136
... For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. AT91CAP7E 136 D[7:0] D[15:8] ...
Page 137
... Byte Select Byte Write NBS0 NWE NWR0 NBS1 NWR1 NBS2 NWR2 NBS3 NWR3 AT91CAP7E D[15:0] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable ...
Page 138
... NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. AT91CAP7E 138 Figure 21-8. NRD_SETUP NRD_PULSE ...
Page 139
... NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 21.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see 8549A–CAP–10/08 AT91CAP7E Figure 21-9). 139 ...
Page 140
... NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro- grammed waveform of NCS may be. AT91CAP7E 140 NRD_PULSE NRD_PULSE ...
Page 141
... Figure 21-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] 8549A–CAP–10/08 t PACC Data Sampling shows the typical read cycle of an LCD module. The read data is valid t t PACC Data Sampling AT91CAP7E after PACC 141 ...
Page 142
... NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 21-12. Write Cycle MCK A [25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NCS_WR_SETUP AT91CAP7E 142 NWE_SETUP NWE_PULSE NCS_WR_PULSE NWE_CYCLE Figure 21-12. The write cycle NWE_HOLD NCS_WR_HOLD 8549A–CAP–10/08 ...
Page 143
... NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 21.8.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set null value leads to unpredictable behavior. 8549A–CAP–10/08 NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE AT91CAP7E Figure 21-13). How- NWE_PULSE NCS_WR_PULSE NWE_CYCLE 143 ...
Page 144
... NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. AT91CAP7E 144 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is shows the waveforms of a write operation with WRITE_MODE set to 0. The data is 8549A– ...
Page 145
... Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] AT91CAP7E Permitted Range Coded Value Effective Value 0 ≤ ≤ 31 128 ≤ ≤ 128+31 0 ≤ ≤ 63 256 ≤ ≤ 256+63 256 ≤ ...
Page 146
... During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..7], NRD lines are all set to 1. Figure 21-16 Select 2. AT91CAP7E 146 gives the default value of timing parameters at reset. Reset Values of Timing Parameters Reset Value ...
Page 147
... If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See 8549A–CAP–10/08 NRD_CYCLE Read to Write Wait State (Figure 21-17). Figure AT91CAP7E NWE_CYCLE Chip Select Wait State 21-19. (Figure 147 ...
Page 148
... Figure 21-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD D[31:0] AT91CAP7E 148 no hold write cycle Early Read wait state no hold write cycle Early Read ...
Page 149
... A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see 8549A–CAP–10/08 no hold read setup = 1 write cycle Early Read (READ_MODE = 0 or READ_MODE = 1) (WRITE_MODE = 1) wait state “Slow Clock Mode” on page AT91CAP7E read cycle 160). 149 ...
Page 150
... MCK cycles during which the data bus remains busy after the rising edge of NCS. Figure 21-20 assuming a data float period of 2 cycles (TDF_CYCLES = 2). ation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. AT91CAP7E 150 Figure 21-16 on page ) for each external memory device is programmed in the ...
Page 151
... D[31:0] Figure 21-21. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS D[31:0] 8549A–CAP–10/08 tpacc TDF = 2 clock cycles NRD controlled read operation tpacc TDF = 3 clock cycles NCS controlled read operation AT91CAP7E 151 ...
Page 152
... TDF optimization. AT91CAP7E 152 shows a read access controlled by NRD, followed by a write access controlled by NRD_HOLD= 4 ...
Page 153
... TDF_CYCLES = 6 5 TDF WAIT STATES Chip Select Wait State read1 hold = 1 TDF_CYCLES = 4 2 TDF WAIT STATES Read to Write Chip Select Wait State Wait State AT91CAP7E read2 setup = 1 read 2 cycle TDF_MODE = 0 (optimization disabled) write2 setup = 1 write2 cycle TDF_MODE = 0 (optimization disabled) 153 ...
Page 154
... The NWAIT signal is assumed response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. AT91CAP7E 154 read1 hold = 1 TDF_CYCLES = 5 ...
Page 155
... Figure 21-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK A [25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal 8549A–CAP–10/08 FROZEN STATE Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 AT91CAP7E Figure 21- Figure 155 ...
Page 156
... Figure 21-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK A [25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 4 NCS 1 NRD NWAIT internally synchronized NWAIT signal AT91CAP7E 156 FROZEN STATE Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD = Assertion is ignored 8549A–CAP–10/08 ...
Page 157
... Figure 21-28. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11) MCK A [25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal 8549A–CAP–10/ Write cycle EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 AT91CAP7E Figure 21-28 and Figure 21-29. After Wait STATE Fig- 157 ...
Page 158
... Figure 21-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS NRD NWAIT internally synchronized NWAIT signal AT91CAP7E 158 Read cycle EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 Wait STATE Assertion is ignored 8549A–CAP–10/08 ...
Page 159
... NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 21-30. NWAIT Latency MCK A [25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWAIT intenally synchronized NWAIT signal 8549A–CAP–10/ minimal pulse length NWAIT latency 2 cycle resynchronization Read cycle EXNW_MODE = READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 AT91CAP7E WAIT STATE Fig- 159 ...
Page 160
... Table 21-6. Read Parameters NRD_SETUP NRD_PULSE NCS_RD_SETUP NCS_RD_PULSE NRD_CYCLE AT91CAP7E 160 illustrates the read and write operations in slow clock mode. They are valid on all Table 21-6 indicates the value of read and write parameters in slow clock mode Read and Write Timing Parameters in Slow Clock Mode ...
Page 161
... This write cycle finishes with the slow clock mode set of parameters after the clock rate transition 8549A–CAP–10/08 illustrates the recommended procedure to properly switch from one mode to the NWE_CYCLE = 3 SLOW CLOCK MODE WRITE AT91CAP7E NWE_CYCLE = 7 NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State ...
Page 162
... Figure 21-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS SLOW CLOCK MODE WRITE AT91CAP7E 162 1 1 IDLE STATE NORMAL MODE WRITE Reload Configuration Wait State 8549A–CAP–10/08 ...
Page 163
... A denotes the address bus of the memory device 2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored. shows the NRD and NCS timings in page mode access. tpa NRD_PULSE NCS_RD_PULSE AT91CAP7E Table 21-7. ) takes longer than the subse- pa Figure 21-34 ...
Page 164
... AT91CAP7E 164 Programming of Read Timings in Page Mode Value Definition ‘ ...
Page 165
... Figure 21-35. Access to Non-sequential Data within the Same Page MCK A[25:3] A[2], A1, A0 NRD NCS D[7:0] 8549A–CAP–10/08 Page address A1 D1 NRD_PULSE NCS_RD_PULSE AT91CAP7E NRD_PULSE 165 ...
Page 166
... CS_number + 0x04 SMC Pulse Register 0x10 x CS_number + 0x08 SMC Cycle Register 0x10 x CS_number + 0x0C SMC Mode Register AT91CAP7E 166 Table 21-9. For each chip select, a set of 4 registers is used to pro- Table 21-9, “CS_number” denotes the chip select number. Name ...
Page 167
... NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles • NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles 8549A–CAP–10/08 SMC_SETUP[0 ..7] Read/Write NCS_RD_SETUP NCS_WR_SETUP AT91CAP7E NRD_SETUP NWE_SETUP 167 ...
Page 168
... In standard read access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page. AT91CAP7E 168 SMC_PULSE[0..7] Read/Write ...
Page 169
... The total read cycle length is the total duration in clock cycles of the read cycle equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals defined as: Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles 8549A–CAP–10/08 SMC_CYCLE[0..7] Read/Write – – – NRD_CYCLE – – – NWE_CYCLE AT91CAP7E – – NRD_CYCLE – – NWE_CYCLE 169 ...
Page 170
... Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. AT91CAP7E 170 SMC_MODE[0..7] Read/Write ...
Page 171
... Standard read is applied. • PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes 8549A–CAP–10/08 Data Bus Width 0 8-bit bus 1 16-bit bus 0 32-bit bus 1 Reserved Page Size 0 4-byte page 1 8-byte page 0 16-byte page 1 32-byte page AT91CAP7E 171 ...
Page 172
... AT91CAP7E 172 8549A–CAP–10/08 ...
Page 173
... Bank Select Signals Row Signal Column Signal SDRAM Write Enable Data Mask Enable Signals Address Bus Data Bus Table 22-2 to Table 22-7 illustrate the SDRAM device memory mapping seen by the AT91CAP7E Type Active Level Output Output High Output Low Output Output Low ...
Page 174
... Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Table 22-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[12:0] Notes: 1. M[1:0] is the byte address inside a 32-bit word. 2. Bk[1] = BA1, Bk[0] = BA0. AT91CAP7E 174 CPU Address Line Row[10:0] Row[10:0] Row[10:0] Row[10:0] CPU Address Line ...
Page 175
... Bk[1] = BA1, Bk[0] = BA0. 8549A–CAP–10/08 CPU Address Line Row[10:0] Row[10:0] Row[10:0] Row[10:0] CPU Address Line Row[11:0] Row[11:0] Row[11:0] Row[11:0] CPU Address Line Row[12:0] Row[12:0] Row[12:0] Row[12:0] AT91CAP7E Column[7:0] Column[8:0] Column[9:0] Column[10: Column[7:0] Column[8:0] Column[9:0] Column[10: Column[7:0] Column[8:0] Column[9:0] Column[10: ...
Page 176
... Register must be set with the value 1562(15.652 μs x 100 MHz) or 781(7.81 μs x 100 MHz). After initialization, the SDRAM devices are fully functional. Note: AT91CAP7E 176 strongly recommended to respect the instructions stated in cess in order to be certain that the subsequent commands issued by the SDRAMC will be taken into account ...
Page 177
... If the next access is a write-sequential access, but the current access boundary page the next access is in another row, then the SDRAM Controller generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing 8549A–CAP–10/ 1st Auto-refresh 8th Auto-refresh AT91CAP7E MRD MRS Command Valid Command 177 ...
Page 178
... For burst access of specified length ( words), access is not anticipated. This case leads to the best performance. If the burst is broken (border, busy mode, etc.), the next access is han- dled as an incrementing burst of unspecified length. AT91CAP7E 178 ) commands. For definition of these timing parameters, refer to the RCD 187 ...
Page 179
... To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (t mand. This is described in 8549A–CAP–10/ CAS = 2 RCD Row n col a col b col c Dna Figure 22-4 below. AT91CAP7E col d col e col f Dnb Dnc Dnd Dne Dnf ) command and the active/read ( com- RCD 179 ...
Page 180
... It is acknowledged by reading the Interrupt Status Register (SDRAMC_ISR). When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the device is busy and the master is held by a wait signal. See AT91CAP7E 180 ...
Page 181
... SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR) and Drive Strength (DS) parameters must be set in the Low Power Register and transmitted to the low-power SDRAM during initialization. 8549A–CAP–10/ AT91CAP7E CAS = 2 RCD col a Row m Dma 181 ...
Page 182
... SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation auto-refresh operations are performed by the SDRAM itself, the SDRAM Controller carries out the refresh operation. The exit procedure is faster than in self-refresh mode. This is described in AT91CAP7E 182 Self Refresh Mode Access Request to the SDRAM Controller Figure 22-7 ...
Page 183
... When this mode is enabled, the application must not access to the SDRAM until a new initializa- tion sequence is done (See This is described in 8549A–CAP–10/ CAS = 2 RCD col a col b col c col d Dna Dnb “SDRAM Device Initialization” on page Figure 22-8. AT91CAP7E col e col f Dnc Dnd Dne Dnf 176). Low Power Mode 183 ...
Page 184
... Figure 22-8. Deep Power-down Mode Behavior SDRAMC_A[12:0] AT91CAP7E 184 SDCS SDCK Row n col c col d RAS CAS SDWE CKE D[31:0] Dnb Dnc Dnd (input 8549A–CAP–10/08 ...
Page 185
... Name Access SDRAMC_MR Read/Write SDRAMC_TR Read/Write SDRAMC_CR Read/Write SDRAMC_HSR Read/Write SDRAMC_LPR Read/Write SDRAMC_IER Write-only SDRAMC_IDR Write-only SDRAMC_IMR Read-only SDRAMC_ISR Read-only SDRAMC_MDR Read − − AT91CAP7E Reset State 0x00000000 0x00000000 0x852372C0 0x00 0x0 – – 0x0 0x0 0x0 − 185 ...
Page 186
... Mode Register. For instance, when this mode is activated, an access to the “SDRAM_Base + offset” address generates an “Extended Load Mode Register” command with the value “offset” written to the SDRAM device Mode Register Deep power-down mode. Enters deep power-down mode. AT91CAP7E 186 SDRAMC_MR Read/Write 0x00000000 – ...
Page 187
... TRC 7 6 DBW CAS • NC: Number of Column Bits 8549A–CAP–10/08 SDRAMC_TR Read/Write 0x00000000 – – – – – – – – COUNT SDRAMC_CR Read/Write 0x852372C0 AT91CAP7E 26 25 – – – – COUNT TRAS 18 17 TRP 10 9 TWR – 16 – 187 ...
Page 188
... DBW: Data Bus Width Reset value is 16 bits 0: Data bus width is 32 bits. 1: Data bus width is 16 bits. • TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15. AT91CAP7E 188 ...
Page 189
... The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory. 0: Decode cycle is disabled. 1: Decode cycle is enabled. 8549A–CAP–10/08 SDRAMC_HSR Read/Write – – – – – – – – – – – – AT91CAP7E – – – – – – – – – – – DA 189 ...
Page 190
... SDRAM. This parameter must be set according to the SDRAM device specification. • DS: Drive Strength (only for low-power SDRAM) DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parame- ter must be set according to the SDRAM device specification. AT91CAP7E 190 SDRAMC_LPR Read/Write 0x0 ...
Page 191
... SDRAMC_IDR Write-only – – – – – – – – – – – – AT91CAP7E – – – – – – – – – – – RES – – – – – – – ...
Page 192
... RES: Refresh Error Status 0: No refresh error has been detected since the register was last read refresh error has been detected since the register was last read. AT91CAP7E 192 SDRAMC_IMR Read-only – – – – ...
Page 193
... MD: Memory Device Type 00 SDRAM 01 Low-power SDRAM 10 Reserved 11 Reserved. 8549A–CAP–10/08 SDRAMC_MDR Read/Write – – – – – – – – – – – – AT91CAP7E – – – – – – – – – – MD 193 ...
Page 194
... AT91CAP7E 194 8549A–CAP–10/08 ...
Page 195
... To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is gener- ated by the peripheral itself. 8549A–CAP–10/08 channels. The full-duplex peripherals feature 19 mono directional chan- 22 The half-duplex peripherals feature 3 bi-directional channels. AT91CAP7E 195 ...
Page 196
... The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and receive parts of each type are programmed differently: the AT91CAP7E 196 PDC Channel A ...
Page 197
... ENDTX flag is set when the PERIPH_TCR register reaches zero. • TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero. These status flags are described in the Peripheral Status Register. 8549A–CAP–10/08 Section 23.3.3 and to the associated peripheral user interface. AT91CAP7E 197 ...
Page 198
... It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR. 23.3.5.4 Transmit Buffer Empty This flag is set when PERIPH_TCR register reaches zero with PERIPH_TNCR also set to zero and the last data has been written into peripheral THR reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR. AT91CAP7E 198 8549A–CAP–10/08 ...
Page 199
... Transfer Status Register Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SPI, etc.) 8549A–CAP–10/08 AT91CAP7E Name Access (1) PERIPH _RPR ...
Page 200
... RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR Stops peripheral data transfer to the receiver 1 - 65535 = Starts peripheral data transfer if corresponding channel is active AT91CAP7E 200 RXPTR RXPTR 13 12 ...