AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 141

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 21-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
21.8.2.2
Figure 21-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
8549A–CAP–10/08
Read is Controlled by NCS (READ_MODE = 0)
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NBS0,NBS1,
NBS2,NBS3,
A0, A1
D[31:0]
D[31:0]
A[25:2]
A[25:2]
MCK
MCK
NRD
NCS
NRD
NCS
Figure 21-11
the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be
sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled
by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates
the rising edge of NCS, whatever the programmed waveform of NRD may be.
shows the typical read cycle of an LCD module. The read data is valid t
t
t
PACC
PACC
Data Sampling
Data Sampling
AT91CAP7E
PACC
after
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