AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 358

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 29-14. Asynchronous Start Bit Detection
Figure 29-15. Preamble Pattern Mismatch
Figure 29-16. Manchester Error Flag
358
AT91CAP7E
Manchester
Manchester
Sampling
Manchester
encoded
encoded
encoded
(16 x)
Clock
data
data
data
sampling points
The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data
at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is
detected, the receiver continues decoding with the same synchronization. If the stream does not
match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next
valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time.
If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming
stream is decoded into NRZ data and passed to USART for processing.
Manchester pattern mismatch. When incoming data stream is passed to the USART, the
receiver is also able to detect Manchester code violation. A code violation is a lack of transition
in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is cleared by
writing the Control Register (US_CR) with the RSTSTA bit at 1. See
ple of Manchester error detection during data phase.
When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data
delimiter are supported. If a valid sync is detected, the received character is written as RXCHR
Txd
Txd
Txd
1
Manchester coding error
2
Preamble Length
3
Preamble Mismatch
4
Preamble Length is set to 8
is set to 4
Detection
Start
and Start Frame Delimiter
Preamble subpacket
were successfully
Preamble Mismatch
SFD
decoded
invalid pattern
Entering USART character area
Elementary character bit time
SFD
Coding Error
Manchester
Figure 29-16
detected
DATA
Figure 29-15
8549A–CAP–10/08
for an exam-
illustrates