AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 511

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8549A–CAP–10/08
22 SDRAM Controller (HSDRAMC) .......................................................... 173
23 Peripheral DMA Controller (PDC) ....................................................... 195
21.42Static Memory Controller (SMC) User Interface ................................................166
22.1Description ..........................................................................................................173
22.2I/O Lines Description ...........................................................................................173
22.3Application Example ............................................................................................173
22.4Software Interface ...............................................................................................173
22.7Product Dependencies ........................................................................................176
22.11Functional Description .......................................................................................177
22.17SDRAM Controller User Interface .....................................................................185
23.1Description ..........................................................................................................195
23.2Block Diagram .....................................................................................................196
23.3Functional Description .........................................................................................196
21.39.2Byte Access Type in Page Mode 164
21.40.3Page Mode Restriction 164
21.41.4Sequential and Non-sequential Accesses 164
21.43.1SMC Setup Register 167
21.44.2SMC Pulse Register 168
21.45.3SMC Cycle Register 169
21.46.4SMC MODE Register 170
22.5.132-bit Memory Data Bus Width 174
22.6.216-bit Memory Data Bus Width 175
22.8.1SDRAM Device Initialization 176
22.9.2I/O Lines 177
22.10.3Interrupt 177
22.12.1SDRAM Controller Write Cycle 177
22.13.2SDRAM Controller Read Cycle 178
22.14.3Border Management 179
22.15.4SDRAM Controller Refresh Cycles 180
22.16.5Power Management 181
22.18.1SDRAMC Mode Register 186
22.19.2SDRAMC Refresh Timer Register 187
22.20.3SDRAMC Configuration Register 187
22.21.4SDRAMC High Speed Register 189
22.22.5SDRAMC Low Power Register 190
22.23.6SDRAMC Interrupt Enable Register 191
22.24.7SDRAMC Interrupt Disable Register 191
22.25.8SDRAMC Interrupt Mask Register 192
22.26.9SDRAMC Interrupt Status Register 192
22.27.10SDRAMC Memory Device Register 193
23.4.1Configuration 196
23.5.2Memory Pointers 197
23.6.3Transfer Counters 197
23.7.4Data Transfers 198
AT91CAP7E
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