AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 103

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19. Bus Matrix
19.1
19.2
19.3
19.3.1
19.3.2
19.3.3
8549A–CAP–10/08
Description
Memory Mapping
Special Bus Granting Mechanism
No Default Master
Last Access Master
Fixed Default Master
The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables par-
allel access paths between multiple AHB masters and slaves in a system, thus increasing the
overall bandwidth. The Bus Matrix interconnects up to 4 AHB Masters to up to 8 AHB Slaves.
The normal latency to connect a master to a slave is one cycle except for the default master of
the accessed slave which is connected directly (zero cycle latency). The Bus Matrix user inter-
face is compliant with ARM
(MATRIX_SFR) that allow the Bus Matrix to support application specific features.
The Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each
AHB Master several memory mappings. In fact, depending on the product, each memory area
may be assigned to several slaves. Booting at the same address while using different AHB
slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that
performs remap action for every master independently.
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism reduces latency at first access of a burst or single
transfer. This bus granting mechanism sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to
its associated default master. A slave can be associated with three kinds of default masters: no
default master, last access master and fixed default master.
At the end of the current access, if no other request is pending, the slave is disconnected from
all masters. No Default Master suits low-power mode.
At the end of the current access, if no other request is pending, the slave remains connected to
the last master that performed an access request.
At the end of the current access, if no other request is pending, the slave connects to its fixed
default master. Unlike last access master, the fixed master does not change unless the user
modifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the
Slave Configuration Registers, one for each slave, that set a default master for each slave. The
Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The
2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed
default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master pro-
vided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user
interface description.
®
Advance Peripheral Bus and provides 6 Special Function Registers
AT91CAP7E
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