AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 69

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.3.3
14.3.3.1
Figure 14-3. General Reset State
8549A–CAP–10/08
Reset States
Backup Supply
backup_nreset
periph_nreset
POR output
proc_nreset
General Reset
(nrst_out)
RSTTYP
SLCK
NRST
MCK
As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system
power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.
The Reset State Manager handles the different reset sources and generates the internal reset
signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The
update of the field RSTTYP is performed when the processor reset is released.
A general reset occurs when VDDBU is powered on. The backup supply POR cell output rises
and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter
is to make sure the Slow Clock oscillator is stable before starting up the device. The length of
startup time is hardcoded to comply with the RC Oscillator startup time of 8 slow clock cycles.
After this time, the processor clock is released at Slow Clock and all the other signals remains
valid for 2 cycles for proper processor and logic reset. Then, all the reset signals are released
and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the
NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0.
When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immedi-
ately asserted, even if the Main Supply POR Cell does not report a Main Supply shut down.
Figure 14-3
Startup Time
shows how the General Reset affects the reset signals.
XXX
Processor Startup
EXTERNAL RESET LENGTH
= 3 cycles
= 2 cycles
0x0 = General Reset
Freq.
Any
AT91CAP7E
XXX
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