DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 687
DF2214BQ16V
Manufacturer Part Number
DF2214BQ16V
Description
IC H8S/2214 MCU FLASH 112-TFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets
1.HS2214ECB62H.pdf
(938 pages)
2.HEWH8E10A.pdf
(19 pages)
3.D12312SVTE25V.pdf
(341 pages)
Specifications of DF2214BQ16V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-TFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2214BQ16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 17.2 shows the timing for transition to and clearance of medium-speed mode.
17.4
17.4.1
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters
sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers
are retained. Other supporting modules do not stop.
17.4.2
Sleep mode is cleared by all interrupts, or with the RES pin, MRES pin or STBY pin.
(1) Clearing with an Interrupt
When an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is
started. Sleep mode will not be cleared if interrupts are disabled, or if interrupts other than NMI
have been masked by the CPU.
(2) Clearing with the RES Pin and MRES Pin
When the RES pin and MRES pin is driven low, the reset state is entered. When the RES pin and
MRES pin is driven high after the prescribed reset input period, the CPU begins reset exception
handling.
φ,
supporting module
clock
Bus master clock
Internal address
bus
Internal write signal
Sleep Mode
Clearing Sleep Mode
Sleep Mode
Figure 17.2 Medium-Speed Mode Transition and Clearance Timing
SBYCR
Medium-speed mode
Rev.4.00 Sep. 18, 2008 Page 625 of 872
Section 17 Power-Down Modes
SBYCR
REJ09B0189-0400
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