DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 26

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
A.1 Instruction List
Table A.1 Data
Transfer Instructions
Table A.2
Arithmetic
Instructions
A.4 Number of
States Required for
Instruction
Execution
Table A.15
Number of Cycles in
Instruction
Execution
Rev.4.00 Sep. 18, 2008 Page xxiv of lx
REJ09B0189-0400
Page
665
669
711
715
716
Revisions (See Manual for Details)
Note added
Note : The STM/LDM instructions may only be used with the ER0
Note added
Note : The TAS instruction may only be used with the ER0, ER1,
Note added
Instruction
LDM*
Note amended
Instruction
STM*
TAS*
Note added
Notes : 4. The STM/LDM instructions may only be used with the
TAS*
LDM*
STM*
3
4
4
Mnemonic
Mnemonic
LDM @SP+,(ERm-ERn)
STM (ERm-ERn),@-SP
TAS @ERd*
to ER6 registers.
ER4, and ER5 registers.
Mnemonic
LDM.L @SP+,
(ERn-ERn+1)
LDM.L @SP+,
(ERn-ERn+2)
LDM.L @SP+,
(ERn-ERn+3)
Mnemonic
STM.L (ERn-ERn+1),
@-SP
STM.L (ERn-ERn+2),
@-SP
STM.L (ERn-ERn+3),
@-SP
TAS @ERd
ER0 to ER6 registers.
2
L
L
B
Instruction Length (Bytes)
Instruction Length (Bytes)
Addressing Mode/
Addressing Mode/
4
Instruction
Fetch
I
2
2
2
Instruction
Fetch
I
2
2
2
2
4
4
Branch
Address
Read
J
Branch
Address
Read
J
(@SP ERn32,SP+4 SP)
Repeated for each register restored
(SP-4 SP,ERn32 @SP)
Repeated for each register saved
@ERd-0→CCR set, (1)→
(<bit 7> of @ERd
Operation
Operation
Stack
Operation
K
4
6
8
Stack
Operation
K
4
6
8
Byte
Data
Access
L
Byte
Data
Access
L
2
— — — — — —
— — — — — —
— —
I H N Z V C
I H N Z V C
Condition Code
Condition Code
Word
Data
Access
M
Word
Data
Access
M
0 —
No. of States *
No. of States *
Advanced
Advanced
Internal
Operation
N
1
1
1
Internal
Operation
N
1
1
1
7/9/11 [1]
7/9/11 [1]
4
1
1