DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 552

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Serial Communication Interface (SCI)
12.3.2
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and stop bits indicating the end of communication. Serial communication
is thus carried out with synchronization established on a character-by-character basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 12.5 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSB-
first order), a parity bit (high or low level), and finally stop bits (high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the
length of one bit, so that the transfer data is latched at the center of each bit.
When the ABCS bit in SEMR0 is set to 1, SCI0 samples the data on the 4th pulse of a clock with a
frequency of 8 times the length of one bit.
Rev.4.00 Sep. 18, 2008 Page 490 of 872
REJ09B0189-0400
Serial
data
1
Operation in Asynchronous Mode
Start
bit
1 bit
0
LSB
Figure 12.5 Data Format in Asynchronous Communication
D0
One unit of transfer data (character or frame)
(Example with 8-Bit Data, Parity, Two Stop Bits)
D1
D2
Transmit/receive data
D3
7 or 8 bits
D4
D5
D6
MSB
D7
Parity
bit
1 bit,
or none
0/1
Stop bit
1
1 or
2 bits
1
Idle state
(mark state)
1