DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 31

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
B.2 Functions
SSR2—Serial
Status Register 2
Page
819
Revisions (See Manual for Details)
Note added
Bit
Initial value
R/W
Notes: 1. Only 0 can be written, to clear the flag.
Transmit Data Register Empty
0
1
2. Flags are only cleared when DISEL is 0 and furthermore the transfer counter is not 0.
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC*
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Receive Data Register Full
0
1
Overrun Error
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC*
[Setting condition]
• When serial reception ends normally and receive data is transferred from
0
1
:
:
:
RSR to RDR
Framing Error
[Clearing condition]
• When 0 is written to ORER after reading ORER = 1
[Setting condition]
• When the next serial reception is completed while RDRF = 1
0
1
R/(W)*
TDRE
[Clearing condition]
• When 0 is written to FER after reading FER = 1
[Setting condition]
• When the SCI checks whether the stop bit at the end of the
Parity Error
receive data when reception ends, and the stop bit is 0
0
1
7
1
2
[Clearing condition]
• When 0 is written to PER after reading PER = 1
[Setting condition]
• When, in reception, the number of 1 bits in the receive data plus
Transmit End
1
the parity bit does not match the parity setting (even or odd)
specified by the O/E bit in SMR
is activated by a TXI interrupt request and writes data to TDR
0
1
2
R/(W)*
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC*
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte serial
Multiprocessor Bit
RDRF
is activated by an RXI interrupt request and reads data from RDR
transmit character
0
1
6
0
[Clearing condition]
• When data with a 0 multiprocessor bit is received
[Setting condition]
• When data with a 1 multiprocessor bit is received
Multiprocessor Bit Transfer
0
1
1
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
R/(W)*
ORER
Rev.4.00 Sep. 18, 2008 Page xxix of lx
5
0
2
1
is activated by a TXI interrupt request and writes data to TDR
R/(W)*
FER
4
0
1
R/(W)*
PER
3
0
1
TEND
R
2
1
REJ09B0189-0400
MPB
R
1
0
MPBT
R/W
0
0