DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 504

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 Watchdog Timer (WDT)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source,
obtained by dividing the system clock (φ) for input to TCNT.
Bit 2
CKS2
0
1
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until
11.2.3
RSTCSR is an 8-bit readable/writable * register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the internal reset
signal caused by a WDT overflow.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
Rev.4.00 Sep. 18, 2008 Page 442 of 872
REJ09B0189-0400
Bit
Initial value :
R/W
Note: * Only 0 can be written, to clear the flag.
overflow occurs.
see section 11.2.4, Notes on Register Access.
Bit 1
CKS1
0
1
0
1
Reset Control/Status Register (RSTCSR)
:
:
R/(W)*
WOVF
Bit 0
CKS0
0
1
0
1
0
1
0
1
7
0
RSTE
R/W
6
0
Clock
φ/2 (Initial value)
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
RSTS
R/W
5
0
—
—
4
1
Overflow Period * (when φ = 10 MHz)
51.2 µs
1.6 ms
3.2 ms
13.2 ms
52.4 ms
209.8 ms
838.8 ms
3.36 s
Description
—
—
3
1
—
—
2
1
—
—
1
1
—
—
0
1