DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 25

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
12.4 SCI Interrupts 518
12.5 Usage Notes
(1) Module Stop
Mode Settings
(8) Restrictions on
Use of DMAC or
DTC
17.6.3 Setting
Oscillation
Stabilization Time
after Clearing
Software Standby
Mode
Table 17.4
Oscillation
Stabilization Time
Settings
18.7 Usage Note
• Characteristics of
the F-ZTAT and
Mask ROM Versions
• General Notes on
Printed Circuit
Board Deign
Page
520
523
630
659
Revisions (See Manual for Details)
Note added
... The TDRE flag is cleared to 0 automatically when data transfer
is performed by the DMAC or DTC*. ...
... The RDRF flag is cleared to 0 automatically when data transfer
is performed by the DMAC or DTC*. ...
Note : * The flag is cleared when DISEL is 0 and furthermore the
Description added
Description added
(b) When RDR is read by the DMAC or DTC, be sure to set the
(c) During data transfers, flags are cleared automatically by DTC
Table amended
STS2 STS1 STS0 Standby Time 16 MHz 13 MHz 10 MHz 8 MHz
0
Title added
Description added
1
: Recommended time setting
activation source to the relevant SCI reception end interrupt
(RXI).
only when the DTC DISEL bit is 0 and furthermore the transfer
counter is not 0. Therefore the CPU must clear the flags when
either DISEL is 1 or when DISEL is 0 and furthermore the
transfer counter is 0. In particular, note that during
transmission, data will not be transmitted correctly unless the
CPU clears the TDRE flag.
0
1
0
1
0
1
0
1
0
1
0
1
transfer counter is not 0.
8192 states
16384 states
32768 states
65536 states
131072 states
262144 states
2048 states
16 states
0.51
1.0
2.0
4.1
16.4
0.13
1.0
8.2
Rev.4.00 Sep. 18, 2008 Page xxiii of lx
0.63
1.3
2.5
5.0
20.2
0.16
1.2
10.1
0.82
1.6
3.3
6.6
26.2
0.20
1.6
13.1
1.0
2.0
4.1
16.4
32.8
0.26
2.0
8.2
6 MHz
1.4
2.7
5.5
21.8
43.7
0.34
2.7
10.9
REJ09B0189-0400
4 MHz
2.0
4.1
16.4
32.8
65.5
0.51
4.0
8.2
2 MHz
4.1
16.4
32.8
65.5
131.1
1.0
8.0
8.2
Unit
ms
µs