DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 19

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
12.3.2 Operation in
Asynchronous Mode
Figure 12.8
Sample Serial
Transmission
Flowchart
Page
494
Revisions (See Manual for Details)
Note added
and clear TDRE flag in SSR to 0
Write transmit data to TDR
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted?
Start transmission
Clear DR to 0 and
Break output?
set DDR to 1
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Yes
Rev.4.00 Sep. 18, 2008 Page xvii of lx
No
No
No
No
[1]
[2]
[3]
[4]
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Serial transmission continuation
[4] Break output at the end of serial
Note: * The TDRE flag check and clear
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC or
DTC* is activated by a transmit
data empty interrupt (TXI) request,
and date is written to TDR.
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
operations are performed
automatically
by DTC only when the DTC
DISEL bit is 0 and furthermore
the transfer counter is not 0.
Therefore the CPU must clear
the TDRE flag when either
DISEL is 1 or when DISEL is 0
and furthermore the transfer
counter is 0.
REJ09B0189-0400