DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 22

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
12.3.4 Operation in
Clocked
Synchronous Mode
Figure 12.21
Sample Serial
Transmission
Flowchart
Rev.4.00 Sep. 18, 2008 Page xx of lx
REJ09B0189-0400
Page
512
Revisions (See Manual for Details)
Note added
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted?
Start transmission
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
No
No
No
[3]
[2]
[1]
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Serial transmission continuation
Note: * The TDRE flag is cleared
The TxD pin is automatically
designated as the transmit data output
pin.
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC* is activated by a transmit data
empty interrupt (TXI) request, and data
is written to TDR.
automatically by DTC only when
the DTC DISEL bit is 0 and
furthermore the transfer counter is
not 0. Therefore the CPU must
clear the TDRE flag when either
DISEL is 1 or when DISEL is 0 and
furthermore the transfer counter is
0.