LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 72
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
UM10375
User manual
5.6.21 Interrupt Priority Register 10
5.6.22 Interrupt Priority Register 11
The IPR10 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 83.
The IPR11 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 84.
Bit
2:0
7:3
10:8
15:11 IP_CT16B0
18:16 Unimplemented
23:19 IP_CT16B1
26:24 Unimplemented
31:27 IP_CT32B0
Bit
2:0
7:3
10:8
15:11 IP_SSP
18:16 Unimplemented
23:19 IP_UART
26:24 Unimplemented
31:27 IP_USBIRQ
Unimplemented
IP_I2C
Unimplemented
IP_CT32B1
Name
Unimplemented
Name
Unimplemented
Interrupt Priority Register 10 (IPR10 - address 0xE000 E428) bit description
Interrupt Priority Register 11 (IPR11 - address 0xE000 E42C) bit description
All information provided in this document is subject to legal disclaimers.
Description
These bits ignore writes, and read as 0.
I2C Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
CT16B0 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
These bits ignore writes, and read as 0.
CT16B1 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
These bits ignore writes, and read as 0.
CT32B0 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
Description
These bits ignore writes, and read as 0.
CT32B1 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
These bits ignore writes, and read as 0.
SSP Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
UART Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
USBIRQ Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
Rev. 2 — 7 July 2010
Chapter 5: LPC13xx Interrupt controller
UM10375
© NXP B.V. 2010. All rights reserved.
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