LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 128

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
9.8 Pin description
9.9 Clocking and power control
UM10375
User manual
9.9.1 Power requirements
9.9.2 Clocks
For an OUT transaction, the USB ATX receives the bi-directional USB_DP and USB_DM
signals of the USB bus. The Serial Interface Engine (SIE) receives the serial data from the
ATX and converts it into a parallel data stream. The parallel data is written to the
corresponding endpoint buffer.
For IN transactions, the SIE reads the parallel data from the endpoint buffer in EP_RAM,
converts it into serial data, and transmits it onto the USB bus using the USB ATX.
Once data has been received or sent, the endpoint buffer can be read or written. The CPU
transfers data between RAM and the endpoint buffer using the register interface. See
Section 9.13 “Functional description”
The device controller can access one USB port.
Table 152. USB device pin description
This section describes the clocking and power management features of the USB Device
Controller.
The USB protocol insists on power management by the device. This becomes very critical
if the device draws power from the bus (bus-powered device). The following constraints
should be met by a bus-powered device:
The USB device controller clocks are shown in
Name
V
USB_CONNECT
USB_FTOGGLE
USB_DP
USB_DM
1. A device in the non-configured state should draw a maximum of 100 mA from the bus.
2. A configured device can draw only up to what is specified in the Max Power field of
3. A suspended device can draw a maximum of 500 μA.
BUS
the configuration descriptor. The maximum value is 500 mA.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Direction
I
O
O
I/O
I/O
for a detailed description.
Description
V
via its corresponding IOCONFIG register, it is driven
HIGH internally.
SoftConnect control signal.
USB 1 ms SoF signal.
Positive differential data.
Negative differential data.
BUS
Chapter 9: LPC13xx USB device controller
status input. When this function is not enabled
Table 153
UM10375
© NXP B.V. 2010. All rights reserved.
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