LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 129

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
9.9.3 Power management support
Table 153. USB device controller clock sources
The usb_clk clock can be either provided by the main clock or a dedicated USB PLL (see
Figure
PDRUNCFG register
To help conserve power, the USB device controller automatically disables PCLK and
USB_MainClk when not in use.
The assertion of USB_Suspend(_N) signal indicates that there was no activity on the USB
bus for the last 3 ms. At this time an interrupt is sent to the processor on which the
software can start preparing the device for suspend.
If there is no activity again for the next 2 ms, the USB_NeedClk signal will go low. This
shuts off the USB_MainClk automatically. Once the USB_MainClk is switched off, internal
registers in the USB clock domain will not be visible to the software.
When the activity is detected on the bus, USB_Suspend(_N) is deactivated and
USB_NeedClk signal is activated. This process is fully combinatorial and hence no
USB_MainClk is required to activate the USB_NeedClk signal.
The usb_clk_enable signal is provided by the SYSAHBCLK bit 14 (see
enables the clock to the USB register block.
In addition, the on-chip device PHY can be powered down in the PDRUNCFG register
(Table
Source
ahb_sys_clk
usb_clk (see
Table
10)
52) if the USB device function is not needed.
3). The USB PLL can be powered down if it is not used for the usb_clk in the
All information provided in this document is subject to legal disclaimers.
Clock name
USB_MainClk USB_MainClk is the 48 MHz ± 500 ppm input clock. This
PCLK
(Table
Rev. 2 — 7 July 2010
52) to conserve power.
Description
This is the system clock. Minimum frequency of this clock is
16 MHz.
clock does not need to be synchronized with the system clock
(PCLK). Gating of this clock is possible by an external control
block using the USB_NeedClk signal. This clock will be used
to recover the 12 MHz clock from the USB bus
Chapter 9: LPC13xx USB device controller
UM10375
© NXP B.V. 2010. All rights reserved.
Table
23) which
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