LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 31
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
UM10375
User manual
3.5.35 System tick counter calibration register
3.5.36 Start logic edge control register 0
Table 39.
Table 40.
The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11)
and 1 (PIO1_0 to PIO1_11) and the lower 8 inputs of port 2 (PIO2_0 to PIO2_7). This
register selects a falling or rising edge on the corresponding PIO input to produce a falling
or rising clock edge, respectively, for the start logic (see
Every bit in the STARTAPRP0 register controls one port input and is connected to one
wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt
0, bit 1 to interrupt 1, etc. (see
register, the top 8 interrupts are contained in the STARTAPRP1 register for total of 40
wake-up interrupts.
Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the
corresponding PIO pin is used to wake up the chip from Deep-sleep mode.
Table 41.
Bit
3:2
4
31:5
Bit
25:0
31:26
Bit
0
Symbol
APRPIO0_0
Symbol
BODINTVAL
BODRSTENA
-
Symbol
CAL
-
BOD control register (BODCTRL, address 0x4004 8150) bit description
System tick timer calibration register (SYSTCKCAL, address 0x4004 8158) bit
description
Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit
description
All information provided in this document is subject to legal disclaimers.
Value
0
1
Value
00
01
10
11
0
1
-
Value
-
Rev. 2 — 7 July 2010
Description
Edge select for start logic input PIO0_0
Falling edge
Rising edge
Table
Description
BOD interrupt level
The interrupt assertion threshold voltage is 1.69 V; the
interrupt de-assertion threshold voltage is 1.84 V.
The interrupt assertion threshold voltage is 2.29 V; the
interrupt de-assertion threshold voltage is 2.44 V.
The interrupt assertion threshold voltage is 2.59 V; the
interrupt de-assertion threshold voltage is 2.74 V.
The interrupt assertion threshold voltage is 2.87 V; the
interrupt de-assertion threshold voltage is 2.98 V.
BOD reset enable
Disable reset function.
Enable reset function.
Reserved
Description
System tick timer calibration value
Reserved
61). The bottom 32 interrupts are contained this
Chapter 3: LPC13xx System configuration
Section
3.9.2).
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0
32 of 333
Reset
value
0x00
0x00
Reset
value
<tbd>
0x00
0x0
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