LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 44

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
3.8.3.3 Wake-up from Deep-sleep mode
3.8.4.1 Power configuration in Deep power-down mode
3.8.4.2 Programming Deep power-down mode
3.8.4 Deep power-down mode
The microcontroller can wake up from Deep-sleep mode in the following ways:
Remark: If the watchdog oscillator is running in Deep-sleep mode, its frequency
determines the wake-up time causing the wake-up time to be longer than waking up with
the IRC.
In Deep power-down mode, power and clocks are shut off to the entire chip with the
exception of the WAKEUP pin. The Deep power-down mode is controlled by the PMU
(see
During Deep power-down mode, the contents of the SRAM and registers are not retained
except for a small amount of data which can be stored in the general purpose registers of
the PMU block.
All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin.
Deep power-down mode has no configuration options. All clocks, the core, and all
peripherals are powered down. Only the WAKEUP pin is powered.
The following steps must be performed to enter Deep power-down mode:
1. Pull the WAKEUP pin externally HIGH.
2. Write one to the DPDEN bit in the PCON register (see
3. Store data to be retained in the general purpose registers
4. Write one to the SLEEPDEEP bit in the ARM Cortex-M3 SCR register.
5. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in
6. Use the ARM WFI instruction.
•
•
•
•
Signal on an external pin. For this purpose, pins PIO0_0 to PIO0_11 and PIO1_0 can
be enabled as inputs to the start logic. The start logic does not require any clocks and
generates the interrupt if enabled in the NVIC to wake up from Deep-sleep mode.
Input signal to the start logic created by a match event on one of the general purpose
timer match outputs. The pin holding the timer match function must be enabled as
start logic input in the NVIC, the corresponding timer must be enabled in the
SYSAHBCLKCTRL register, and the watchdog oscillator must be running in
Deep-sleep mode (for details see
Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the
PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL
register
Reset from the watchdog timer. In this case, the watchdog oscillator must be running
in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in
the SYSAHBCLKCTRL register.
the PDRUNCFG register before entering Deep power-down mode.
Chapter
(Table
4).
All information provided in this document is subject to legal disclaimers.
39).
Rev. 2 — 7 July 2010
Section
Chapter 3: LPC13xx System configuration
3.9.3).
Table
(Table
58).
59).
UM10375
© NXP B.V. 2010. All rights reserved.
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