LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 42

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
3.8.1.1 Power configuration in Active mode
3.8.2.1 Power configuration in Sleep mode
3.8.2.2 Programming Sleep mode
3.8.2.3 Wake-up from Sleep mode
3.8.2 Sleep mode
Power consumption in Active mode is determined by the following configuration choices:
In Sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution of
instructions is suspended until either a reset or an interrupt occurs.
Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue
operation during Sleep mode and may generate interrupts to cause the processor to
resume execution. Sleep mode eliminates dynamic power used by the processor itself,
memory systems and related controllers, and internal buses. The processor state and
registers, peripheral registers, and internal SRAM values are maintained, and the logic
levels of the pins remain static.
Power consumption in Sleep mode is configured by the same settings as in Active mode:
The following steps must be performed to enter Sleep mode:
Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the
processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns
to its original power configuration defined by the contents of the PDRUNCFG and the
SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default
configuration in Active mode.
1. The DPDEN bit in the PCON register must be set to zero
2. The SLEEPDEEP bit in the ARM Cortex-M3 SCR register must be set to zero.
3. Use the ARM Cortex-M0 Wait-For-Interrupt (WFI) instruction.
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The SYSAHBCLKCTRL register controls which memories and peripherals are
running
The power to various analog blocks (USB, PLL, oscillators, the ADC, the BOD circuit,
and the flash block) can be controlled at any time individually through the
PDRUNCFG register
The clock source for the system clock can be selected from the IRC (default), the
system oscillator, or the watchdog oscillator (see
The system clock frequency can be selected by the SYSPLLCTRL
SYSAHBCLKDIV register
Selected peripherals (UART, SSP0/1, WDT) use individual peripheral clocks with their
own clock dividers. The peripheral clocks can be shut down through the
corresponding clock divider registers
The clock remains running.
The system clock frequency remains the same as in Active mode, but the processor is
not clocked.
Analog and digital peripherals are selected as in Active mode.
(Table
All information provided in this document is subject to legal disclaimers.
23).
Rev. 2 — 7 July 2010
(Table
(Table
52).
22).
(Table 24
Chapter 3: LPC13xx System configuration
to
Figure 3
Table
27).
(Table
and related registers).
58).
UM10375
© NXP B.V. 2010. All rights reserved.
(Table
8) and the
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