LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 172

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
11.6.6 UART FIFO Control Register (U0FCR - 0x4000 8008, Write Only)
11.6.7 UART Line Control Register (U0LCR - 0x4000 800C)
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U0THR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U0THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART THR FIFO has held two or more characters at one time and
currently, the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or
a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).
The U0FCR controls the operation of the UART RX and TX FIFOs.
Table 194. UART FIFO Control Register (U0FCR - address 0x4000 8008, Write Only) bit
The U0LCR determines the format of the data character that is to be transmitted or
received.
Table 195. UART Line Control Register (U0LCR - address 0x4000 800C) bit description
Bit
0
1
2
3
5:4
7:6
31:8 -
Bit
1:0
Symbol Value Description
Word
Length
Select
Symbol
FIFO
Enable
RX FIFO
TX FIFO
-
Reset
Reset
-
RX
Trigger
Level
description
00
01
10
11
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
-
-
00
01
10
11
5-bit character length.
6-bit character length.
7-bit character length.
8-bit character length.
UART FIFOs are disabled. Must not be used in the application.
Active high enable for both UART Rx and TX FIFOs and
U0FCR[7:1] access. This bit must be set for proper UART
operation. Any transition on this bit will automatically clear the
UART FIFOs.
No impact on either of UART FIFOs.
Writing a logic 1 to U0FCR[1] will clear all bytes in UART Rx FIFO,
reset the pointer logic. This bit is self-clearing.
No impact on either of UART FIFOs.
Writing a logic 1 to U0FCR[2] will clear all bytes in UART TX
FIFO, reset the pointer logic. This bit is self-clearing.
Reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
These two bits determine how many receiver UART FIFO
characters must be written before an interrupt is activated.
Trigger level 0 (1 character or 0x01).
Trigger level 1 (4 characters or 0x04).
Trigger level 2 (8 characters or 0x08).
Trigger level 3 (14 characters or 0x0E).
Reserved
Rev. 2 — 7 July 2010
Chapter 11: LPC13xx UART
UM10375
© NXP B.V. 2010. All rights reserved.
174 of 333
Reset
value
0
0
0
0
NA
0
-
Reset
Value
0