LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 110

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
7.4 Pin description
UM10375
User manual
In
and special function pins appear at the end.
The default function of each pin is always the first function listed in the description column
or the first function of each pin symbol. Each pin function can be set through the
corresponding IOCON register (see
Fig 9.
PIO0_1/CLKOUT/CT32B0_MAT2
Table 136
PIO0_2/SSEL/CT16B0_CAP0
PIO1_8/CT16B1_CAP0
LPC1311/13 HVQFN33 package
and
RESET/PIO0_0
All information provided in this document is subject to legal disclaimers.
PIO2_0/DTR
Table
index area
terminal 1
XTALOUT
XTALIN
V
137, the pins are listed in order of their port number. Supply pins
DD
Rev. 2 — 7 July 2010
1
2
3
4
5
6
7
8
Transparent top view
LPC1311FHN33
LPC1313FHN33
Table
33 V
SS
91).
Chapter 7: LPC13xx Pin configuration
24
23
22
21
20
19
18
17
002aae517
R/PIO1_2/AD3/CT32B1_MAT1
R/PIO1_1/AD2/CT32B1_MAT0
R/PIO1_0/AD1/CT32B1_CAP0
R/PIO0_11/AD0/CT32B0_MAT3
PIO1_10/AD6/CT16B1_MAT1
SWCLK/PIO0_10/SCK/CT16B0_MAT2
PIO0_9/MOSI/CT16B0_MAT1/SWO
PIO0_8/MISO/CT16B0_MAT0
UM10375
© NXP B.V. 2010. All rights reserved.
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