LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 323

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
21.4 Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Masked write operation to the GPIODATA
Fig 11. Masked read operation . . . . . . . . . . . . . . . . . . .125
Fig 12. USB device controller block diagram . . . . . . . .128
Fig 13. USB SoftConnect interfacing . . . . . . . . . . . . . . .129
Fig 14. USB clocking . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Fig 15. USB device driver pointer structure . . . . . . . . . .157
Fig 16. Auto-RTS Functional Timing . . . . . . . . . . . . . . .177
Fig 17. Auto-CTS Functional Timing . . . . . . . . . . . . . . .178
Fig 18. Auto-baud a) mode 0 and b) mode 1 waveform 183
Fig 19. Algorithm for setting UART dividers. . . . . . . . . .185
Fig 20. UART block diagram . . . . . . . . . . . . . . . . . . . . .191
Fig 21. I
Fig 22. Format in the Master Transmitter mode. . . . . . .203
Fig 23. Format of Master Receiver mode . . . . . . . . . . .204
Fig 24. A Master Receiver switches to Master Transmitter
Fig 25. Format of Slave Receiver mode . . . . . . . . . . . .205
Fig 26. Format of Slave Transmitter mode . . . . . . . . . .205
Fig 27. I
Fig 28. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .208
Fig 29. Serial clock synchronization. . . . . . . . . . . . . . . .208
Fig 30. Format and states in the Master Transmitter
Fig 31. Format and states in the Master Receiver
Fig 32. Format and states in the Slave Receiver mode .220
Fig 33. Format and states in the Slave Transmitter
Fig 34. Simultaneous Repeated START conditions from two
Fig 35. Forced access to a busy I
Fig 36. Recovering from a bus obstruction caused by a
Fig 37. Texas Instruments Synchronous Serial Frame
Fig 38. SPI frame format with CPOL=0 and CPHA=0 (a)
Fig 39. SPI frame format with CPOL=0 and CPHA=1 . .245
Fig 40. SPI frame format with CPOL = 1 and CPHA = 0 (a)
Fig 41. SPI Frame Format with CPOL = 1 and
Fig 42. Microwire frame format (single transfer) . . . . . .248
Fig 43. Microwire frame format (continuos transfers) . .248
Fig 44. Microwire frame format setup and hold details .249
UM10375
User manual
LPC13xx block diagram . . . . . . . . . . . . . . . . . . . . .7
LPC13xx memory map . . . . . . . . . . . . . . . . . . . . .9
LPC13xx CGU block diagram . . . . . . . . . . . . . . .13
System and USB PLL block diagram. . . . . . . . . .47
Standard I/O pin configuration . . . . . . . . . . . . . . .78
LPC1343 LQFP48 package . . . . . . . . . . . . . . . .109
LPC1342/43 HVQFN33 package. . . . . . . . . . . . 110
LPC1313 LQFP48 package . . . . . . . . . . . . . . . . 111
LPC1311/13 HVQFN33 package . . . . . . . . . . . . 112
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
after sending Repeated START . . . . . . . . . . . . .204
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
LOW level on SDA . . . . . . . . . . . . . . . . . . . . . . .226
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer. . . . . . . . . . . . . . . . . . . . .243
Single and b) Continuous Transfer) . . . . . . . . . .244
Single and b) Continuous Transfer) . . . . . . . . . .246
CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
2
2
C-bus configuration . . . . . . . . . . . . . . . . . . . . .193
C serial interface block diagram . . . . . . . . . . .206
2
C-bus . . . . . . . . . . .225
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Fig 45. Sample PWM waveforms with a PWM cycle length
Fig 46. A timer cycle in which PR=2, MRx=6, and both
Fig 47. A timer cycle in which PR=2, MRx=6, and both
Fig 48. 16-bit counter/timer block diagram . . . . . . . . . . 261
Fig 49. Sample PWM waveforms with a PWM cycle length
Fig 50. A timer cycle in which PR=2, MRx=6, and both
Fig 51. A timer cycle in which PR=2, MRx=6, and both
Fig 52. 32-bit counter/timer block diagram . . . . . . . . . . 273
Fig 53. System tick timer block diagram . . . . . . . . . . . . 275
Fig 54. Watchdog block diagram. . . . . . . . . . . . . . . . . . 283
Fig 55. Boot process flowchart . . . . . . . . . . . . . . . . . . . 296
Fig 56. IAP parameter passing . . . . . . . . . . . . . . . . . . . 309
Chapter 21: LPC13xx Supplementary information
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . . 260
interrupt and reset on match are enabled . . . . . 260
interrupt and stop on match are enabled . . . . . 260
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . . 272
interrupt and reset on match are enabled . . . . . 272
interrupt and stop on match are enabled . . . . . 272
UM10375
© NXP B.V. 2010. All rights reserved.
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