LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 7

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

2.1 How to read this chapter
2.2 Memory map
UM10375
User manual
See
Table 2.
Figure 2
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
On the LPC13xx, the GPIO ports are the only AHB peripherals. The APB peripheral area
is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This allows simplifying the address decoding for each
peripheral.
All peripheral register addresses are 32-bit word aligned regardless of their size. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
Part
LPC1311
LPC1313
LPC1342
LPC1343
UM10375
Chapter 2: LPC13xx Memory mapping
Rev. 2 — 7 July 2010
Table 2
shows the memory and peripheral address space of the LPC13xx.
LPC13xx memory configuration
for LPC13xx memory configurations:
Flash Address range
8 kB
32 kB
16 kB
32 kB
All information provided in this document is subject to legal disclaimers.
0x0000 0000 - 0x0000 1FFF
0x0000 0000 - 0x0000 7FFF
0x0000 0000 - 0x0000 3FFF
0x0000 0000 - 0x0000 7FFF
Rev. 2 — 7 July 2010
SRAM
4 kB
8 kB
4 kB
8 kB
Address range
0x1000 0000 - 0x1000 0FFF
0x1000 0000 - 0x1000 1FFF
0x1000 0000 - 0x1000 0FFF
0x1000 0000 - 0x1000 1FFF
© NXP B.V. 2010. All rights reserved.
User manual
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