LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 117
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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8.1 How to read this chapter
Table 138. GPIO configuration
8.2 Features
8.3 Pin description
8.4 Register description
UM10375
User manual
Part
LPC1311
LPC1313 LQFP48
LPC1313 HVQFN33
LPC1342 HVQFN33
LPC1343 LQFP48
Package
HVQFN33
HVQFN33
The number of GPIO pins available on each port depends on the LPC13xx part and the
package. See
GPIO port 0
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_5
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_3
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
Table 139. GPIO pin description
[1]
Each GPIO register can be up to 12 bits wide and can be read or written using word or
half-word operations at word addresses.
Pin
PIO0_0 to PIO0_11
PIO1_0 to PIO1_11
PIO2_0 to PIO2_11
PIO3_0 to PIO3_11
•
•
•
•
•
•
UM10375
Chapter 8: LPC13xx General Purpose I/O (GPIO)
Rev. 2 — 7 July 2010
GPIO pins can be configured as input or output by software.
Each individual port pin can serve as an edge- or level-sensitive interrupt request.
Interrupts can be configured on single falling or rising edges and on both edges.
Level-sensitive interrupt pins can be HIGH- or LOW-active.
All GPIO pins are inputs by default.
Reading and writing of data registers are masked by address bits 13:2.
The pin configuration depends on the LPC13xx package (see
Table 138
All information provided in this document is subject to legal disclaimers.
GPIO port 1
Rev. 2 — 7 July 2010
for available GPIO pins:
I/O
I/O
I/O
I/O
Type
[1]
Description
GPIO port 0 input/output pins.
GPIO port 1 input/output pins.
GPIO port 2 input/output pins.
GPIO port 3 input/output pins.
GPIO port 2
Table
GPIO port 3
PIO3_2; PIO3_4; PIO3_5 28
PIO3_2; PIO3_4; PIO3_5 28
PIO3_2
PIO3_2
138).
© NXP B.V. 2010. All rights reserved.
User manual
119 of 333
Total
GPIO
pins
42
26
40
26
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