LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 239

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
13.7.7 SSP0 Raw Interrupt Status Register (SSP0RIS - 0x4004 0018)
13.7.8 SSP0 Masked Interrupt Status Register (SSP0MIS - 0x4004 001C)
Table 240: SSP0 Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4004 0014) bit
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSP0IMSC.
Table 241: SSP0 Raw Interrupt Status register (SSP0RIS - address 0x4004 0018) bit
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the SSP0IMSC. When an SSP interrupt occurs, the interrupt service routine
should read this register to determine the cause(s) of the interrupt.
Bit
0
1
2
3
31:4
Bit
0
1
2
3
31:4
Symbol
RORIM
RTIM
RXIM
TXIM
-
Symbol
RORRIS
RTRIS
RXRIS
TXRIS
-
description
description
All information provided in this document is subject to legal disclaimers.
Description
Software should set this bit to enable interrupt when a Receive
Overrun occurs, that is, when the Rx FIFO is full and another frame is
completely received. The ARM spec implies that the preceding frame
data is overwritten by the new frame data when this occurs.
Software should set this bit to enable interrupt when a Receive
Time-out condition occurs. A Receive Time-out occurs when the Rx
FIFO is not empty, and no has not been read for a time-out period.
The time-out period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR ×
[SCR+1]).
Software should set this bit to enable interrupt when the Rx FIFO is at
least half full.
Software should set this bit to enable interrupt when the Tx FIFO is at
least half empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
This bit is 1 if another frame was completely received while the
RxFIFO was full. The ARM spec implies that the preceding
frame data is overwritten by the new frame data when this
occurs.
This bit is 1 if the Rx FIFO is not empty, and has not been read
for a time-out period. The time-out period is the same for
master and slave modes and is determined by the SSP bit
rate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).
This bit is 1 if the Rx FIFO is at least half full.
This bit is 1 if the Tx FIFO is at least half empty.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 2 — 7 July 2010
Chapter 13: LPC13xx SSP
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0
0
0
1
NA
241 of 333
Reset
value
0
0
0
0
NA